Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 2 | /* |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 3 | * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | / { |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 7 | cpus { |
| 8 | cpu@0 { |
| 9 | cpu0-supply = <&dcdc2_reg>; |
| 10 | }; |
| 11 | }; |
| 12 | |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 13 | memory@80000000 { |
| 14 | device_type = "memory"; |
| 15 | reg = <0x80000000 0x10000000>; /* 256 MB */ |
| 16 | }; |
| 17 | |
Lokesh Vutla | e302aa1 | 2016-05-16 11:24:25 +0530 | [diff] [blame] | 18 | chosen { |
| 19 | stdout-path = &uart0; |
| 20 | tick-timer = &timer2; |
| 21 | }; |
| 22 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 23 | leds { |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 24 | pinctrl-names = "default"; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 25 | pinctrl-0 = <&user_leds_s0>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 26 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 27 | compatible = "gpio-leds"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 28 | |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 29 | led2 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 30 | label = "beaglebone:green:heartbeat"; |
| 31 | gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; |
| 32 | linux,default-trigger = "heartbeat"; |
| 33 | default-state = "off"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 34 | }; |
| 35 | |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 36 | led3 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 37 | label = "beaglebone:green:mmc0"; |
| 38 | gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; |
| 39 | linux,default-trigger = "mmc0"; |
| 40 | default-state = "off"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 41 | }; |
| 42 | |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 43 | led4 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 44 | label = "beaglebone:green:usr2"; |
| 45 | gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; |
| 46 | linux,default-trigger = "cpu0"; |
| 47 | default-state = "off"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 48 | }; |
| 49 | |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 50 | led5 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 51 | label = "beaglebone:green:usr3"; |
| 52 | gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; |
| 53 | linux,default-trigger = "mmc1"; |
| 54 | default-state = "off"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 55 | }; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 56 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 57 | |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 58 | vmmcsd_fixed: fixedregulator0 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 59 | compatible = "regulator-fixed"; |
| 60 | regulator-name = "vmmcsd_fixed"; |
| 61 | regulator-min-microvolt = <3300000>; |
| 62 | regulator-max-microvolt = <3300000>; |
| 63 | }; |
| 64 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 65 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 66 | &am33xx_pinmux { |
| 67 | pinctrl-names = "default"; |
| 68 | pinctrl-0 = <&clkout2_pin>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 69 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 70 | user_leds_s0: user_leds_s0 { |
| 71 | pinctrl-single,pins = < |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 72 | AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ |
| 73 | AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ |
| 74 | AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ |
| 75 | AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 76 | >; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 77 | }; |
| 78 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 79 | i2c0_pins: pinmux_i2c0_pins { |
| 80 | pinctrl-single,pins = < |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 81 | AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 82 | AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 83 | >; |
| 84 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 85 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 86 | i2c2_pins: pinmux_i2c2_pins { |
| 87 | pinctrl-single,pins = < |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 88 | AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ |
| 89 | AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 90 | >; |
| 91 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 92 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 93 | uart0_pins: pinmux_uart0_pins { |
| 94 | pinctrl-single,pins = < |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 95 | AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) |
| 96 | AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 97 | >; |
| 98 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 99 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 100 | clkout2_pin: pinmux_clkout2_pin { |
| 101 | pinctrl-single,pins = < |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 102 | AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 103 | >; |
| 104 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 105 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 106 | cpsw_default: cpsw_default { |
| 107 | pinctrl-single,pins = < |
| 108 | /* Slave 1 */ |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 109 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) |
| 110 | AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 111 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) |
| 112 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 113 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 114 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 115 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 116 | AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) |
| 117 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) |
| 118 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) |
| 119 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) |
| 120 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) |
| 121 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 122 | >; |
| 123 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 124 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 125 | cpsw_sleep: cpsw_sleep { |
| 126 | pinctrl-single,pins = < |
| 127 | /* Slave 1 reset value */ |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 128 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 129 | AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 130 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 131 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 132 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 133 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 134 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 135 | AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 136 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 137 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 138 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 139 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 140 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 141 | >; |
| 142 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 143 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 144 | davinci_mdio_default: davinci_mdio_default { |
| 145 | pinctrl-single,pins = < |
| 146 | /* MDIO */ |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 147 | AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) |
| 148 | AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 149 | >; |
| 150 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 151 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 152 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 153 | pinctrl-single,pins = < |
| 154 | /* MDIO reset value */ |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 155 | AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 156 | AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 157 | >; |
| 158 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 159 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 160 | mmc1_pins: pinmux_mmc1_pins { |
| 161 | pinctrl-single,pins = < |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 162 | AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ |
| 163 | AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) |
| 164 | AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) |
| 165 | AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) |
| 166 | AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) |
| 167 | AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) |
| 168 | AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 169 | >; |
| 170 | }; |
| 171 | |
| 172 | emmc_pins: pinmux_emmc_pins { |
| 173 | pinctrl-single,pins = < |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 174 | AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ |
| 175 | AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ |
| 176 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ |
| 177 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ |
| 178 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ |
| 179 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ |
| 180 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ |
| 181 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ |
| 182 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ |
| 183 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 184 | >; |
| 185 | }; |
| 186 | }; |
| 187 | |
| 188 | &uart0 { |
| 189 | pinctrl-names = "default"; |
| 190 | pinctrl-0 = <&uart0_pins>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 191 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 192 | status = "okay"; |
| 193 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 194 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 195 | &usb0 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 196 | dr_mode = "peripheral"; |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 197 | interrupts-extended = <&intc 18 &tps 0>; |
| 198 | interrupt-names = "mc", "vbus"; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 199 | }; |
| 200 | |
| 201 | &usb1 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 202 | dr_mode = "host"; |
| 203 | }; |
| 204 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 205 | &i2c0 { |
| 206 | pinctrl-names = "default"; |
| 207 | pinctrl-0 = <&i2c0_pins>; |
| 208 | |
| 209 | status = "okay"; |
| 210 | clock-frequency = <400000>; |
| 211 | |
| 212 | tps: tps@24 { |
| 213 | reg = <0x24>; |
| 214 | }; |
| 215 | |
| 216 | baseboard_eeprom: baseboard_eeprom@50 { |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 217 | compatible = "atmel,24c256"; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 218 | reg = <0x50>; |
| 219 | |
| 220 | #address-cells = <1>; |
| 221 | #size-cells = <1>; |
| 222 | baseboard_data: baseboard_data@0 { |
| 223 | reg = <0 0x100>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 224 | }; |
| 225 | }; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 226 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 227 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 228 | &i2c2 { |
| 229 | pinctrl-names = "default"; |
| 230 | pinctrl-0 = <&i2c2_pins>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 231 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 232 | status = "okay"; |
| 233 | clock-frequency = <100000>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 234 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 235 | cape_eeprom0: cape_eeprom0@54 { |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 236 | compatible = "atmel,24c256"; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 237 | reg = <0x54>; |
| 238 | #address-cells = <1>; |
| 239 | #size-cells = <1>; |
| 240 | cape0_data: cape_data@0 { |
| 241 | reg = <0 0x100>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 242 | }; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 243 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 244 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 245 | cape_eeprom1: cape_eeprom1@55 { |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 246 | compatible = "atmel,24c256"; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 247 | reg = <0x55>; |
| 248 | #address-cells = <1>; |
| 249 | #size-cells = <1>; |
| 250 | cape1_data: cape_data@0 { |
| 251 | reg = <0 0x100>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 252 | }; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 253 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 254 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 255 | cape_eeprom2: cape_eeprom2@56 { |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 256 | compatible = "atmel,24c256"; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 257 | reg = <0x56>; |
| 258 | #address-cells = <1>; |
| 259 | #size-cells = <1>; |
| 260 | cape2_data: cape_data@0 { |
| 261 | reg = <0 0x100>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 262 | }; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 263 | }; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 264 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 265 | cape_eeprom3: cape_eeprom3@57 { |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 266 | compatible = "atmel,24c256"; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 267 | reg = <0x57>; |
| 268 | #address-cells = <1>; |
| 269 | #size-cells = <1>; |
| 270 | cape3_data: cape_data@0 { |
| 271 | reg = <0 0x100>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 272 | }; |
| 273 | }; |
| 274 | }; |
| 275 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 276 | |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 277 | /include/ "tps65217.dtsi" |
| 278 | |
| 279 | &tps { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 280 | /* |
| 281 | * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only |
| 282 | * mode") at poweroff. Most BeagleBone versions do not support RTC-only |
| 283 | * mode and risk hardware damage if this mode is entered. |
| 284 | * |
| 285 | * For details, see linux-omap mailing list May 2015 thread |
| 286 | * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller |
| 287 | * In particular, messages: |
| 288 | * http://www.spinics.net/lists/linux-omap/msg118585.html |
| 289 | * http://www.spinics.net/lists/linux-omap/msg118615.html |
| 290 | * |
| 291 | * You can override this later with |
| 292 | * &tps { /delete-property/ ti,pmic-shutdown-controller; } |
| 293 | * if you want to use RTC-only mode and made sure you are not affected |
| 294 | * by the hardware problems. (Tip: double-check by performing a current |
| 295 | * measurement after shutdown: it should be less than 1 mA.) |
| 296 | */ |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 297 | |
| 298 | interrupts = <7>; /* NMI */ |
| 299 | interrupt-parent = <&intc>; |
| 300 | |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 301 | ti,pmic-shutdown-controller; |
| 302 | |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 303 | charger { |
| 304 | status = "okay"; |
| 305 | }; |
| 306 | |
| 307 | pwrbutton { |
| 308 | status = "okay"; |
| 309 | }; |
| 310 | |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 311 | regulators { |
| 312 | dcdc1_reg: regulator@0 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 313 | regulator-name = "vdds_dpr"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 314 | regulator-always-on; |
| 315 | }; |
| 316 | |
| 317 | dcdc2_reg: regulator@1 { |
| 318 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| 319 | regulator-name = "vdd_mpu"; |
| 320 | regulator-min-microvolt = <925000>; |
Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 321 | regulator-max-microvolt = <1351500>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 322 | regulator-boot-on; |
| 323 | regulator-always-on; |
| 324 | }; |
| 325 | |
| 326 | dcdc3_reg: regulator@2 { |
| 327 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| 328 | regulator-name = "vdd_core"; |
| 329 | regulator-min-microvolt = <925000>; |
| 330 | regulator-max-microvolt = <1150000>; |
| 331 | regulator-boot-on; |
| 332 | regulator-always-on; |
| 333 | }; |
| 334 | |
| 335 | ldo1_reg: regulator@3 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 336 | regulator-name = "vio,vrtc,vdds"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 337 | regulator-always-on; |
| 338 | }; |
| 339 | |
| 340 | ldo2_reg: regulator@4 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 341 | regulator-name = "vdd_3v3aux"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 342 | regulator-always-on; |
| 343 | }; |
| 344 | |
| 345 | ldo3_reg: regulator@5 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 346 | regulator-name = "vdd_1v8"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 347 | regulator-always-on; |
| 348 | }; |
| 349 | |
| 350 | ldo4_reg: regulator@6 { |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 351 | regulator-name = "vdd_3v3a"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 352 | regulator-always-on; |
| 353 | }; |
| 354 | }; |
| 355 | }; |
| 356 | |
| 357 | &cpsw_emac0 { |
Grygorii Strashko | a6f37dc | 2019-08-31 10:30:34 +0300 | [diff] [blame] | 358 | phy-handle = <ðphy0>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 359 | phy-mode = "mii"; |
| 360 | }; |
| 361 | |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 362 | &mac { |
Grygorii Strashko | a6f37dc | 2019-08-31 10:30:34 +0300 | [diff] [blame] | 363 | slaves = <1>; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 364 | pinctrl-names = "default", "sleep"; |
| 365 | pinctrl-0 = <&cpsw_default>; |
| 366 | pinctrl-1 = <&cpsw_sleep>; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 367 | status = "okay"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 368 | }; |
| 369 | |
| 370 | &davinci_mdio { |
| 371 | pinctrl-names = "default", "sleep"; |
| 372 | pinctrl-0 = <&davinci_mdio_default>; |
| 373 | pinctrl-1 = <&davinci_mdio_sleep>; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 374 | status = "okay"; |
Grygorii Strashko | a6f37dc | 2019-08-31 10:30:34 +0300 | [diff] [blame] | 375 | |
| 376 | ethphy0: ethernet-phy@0 { |
| 377 | reg = <0>; |
| 378 | }; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 379 | }; |
| 380 | |
| 381 | &mmc1 { |
| 382 | status = "okay"; |
| 383 | bus-width = <0x4>; |
| 384 | pinctrl-names = "default"; |
| 385 | pinctrl-0 = <&mmc1_pins>; |
Mugunthan V N | 4bbfcc3 | 2016-05-16 11:24:27 +0530 | [diff] [blame] | 386 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; |
Tom Rini | 5ba1596 | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 387 | }; |
| 388 | |
| 389 | &aes { |
| 390 | status = "okay"; |
| 391 | }; |
| 392 | |
| 393 | &sham { |
| 394 | status = "okay"; |
Simon Glass | b37e815 | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 395 | }; |
Dario Binacchi | 9565795 | 2021-06-02 22:38:03 +0200 | [diff] [blame] | 396 | |
| 397 | &rtc { |
| 398 | clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; |
| 399 | clock-names = "ext-clk", "int-clk"; |
Paul Barker | 273f51d | 2022-04-11 15:41:59 +0000 | [diff] [blame] | 400 | system-power-controller; |
| 401 | }; |
| 402 | |
| 403 | &pruss_tm { |
| 404 | status = "okay"; |
Dario Binacchi | 9565795 | 2021-06-02 22:38:03 +0200 | [diff] [blame] | 405 | }; |