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git01.mediatek.com / filogic / uboot / 88b3ecf404852a421426357102cb8899034b3144 / . / arch / arm / dts / ast2600.dtsi
blob: b8fe966c7dc1109df961fb3987fdef21ccfc5321 [file] [log] [blame]
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include "skeleton.dtsi"
4
5/ {
6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2600";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 aliases {
13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c6 = &i2c6;
20 i2c7 = &i2c7;
21 i2c8 = &i2c8;
22 i2c9 = &i2c9;
23 i2c10 = &i2c10;
24 i2c11 = &i2c11;
25 i2c12 = &i2c12;
26 i2c13 = &i2c13;
27 i2c14 = &i2c14;
28 i2c15 = &i2c15;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 serial6 = &uart7;
36 serial7 = &uart8;
37 serial8 = &uart9;
38 serial9 = &uart10;
39 serial10 = &uart11;
40 serial11 = &uart12;
41 serial12 = &uart13;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "aspeed,ast2600-smp";
48
49 cpu@0 {
50 compatible = "arm,cortex-a7";
51 device_type = "cpu";
52 reg = <0xf00>;
53 };
54
55 cpu@1 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0xf01>;
59 };
60
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupt-parent = <&gic>;
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
70 };
71
72 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 gfx_memory: framebuffer {
78 size = <0x01000000>;
79 alignment = <0x01000000>;
80 compatible = "shared-dma-pool";
81 reusable;
82 };
83
84 video_memory: video {
85 size = <0x04000000>;
86 alignment = <0x01000000>;
87 compatible = "shared-dma-pool";
88 no-map;
89 };
90 };
91
92 ahb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 ranges;
98
99 gic: interrupt-controller@40461000 {
100 compatible = "arm,cortex-a7-gic";
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&gic>;
105 reg = <0x40461000 0x1000>,
106 <0x40462000 0x1000>,
107 <0x40464000 0x2000>,
108 <0x40466000 0x2000>;
109 };
110
111 ahbc: ahbc@1e600000 {
112 compatible = "aspeed,aspeed-ahbc";
113 reg = < 0x1e600000 0x100>;
114 };
115
116 fmc: flash-controller@1e620000 {
117 reg = < 0x1e620000 0xc4
118 0x20000000 0x10000000 >;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "aspeed,ast2600-fmc";
122 status = "disabled";
123 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&scu ASPEED_CLK_AHB>;
125 num-cs = <3>;
126 flash@0 {
127 reg = < 0 >;
128 compatible = "jedec,spi-nor";
129 status = "disabled";
130 };
131 flash@1 {
132 reg = < 1 >;
133 compatible = "jedec,spi-nor";
134 status = "disabled";
135 };
136 flash@2 {
137 reg = < 2 >;
138 compatible = "jedec,spi-nor";
139 status = "disabled";
140 };
141 };
142
143 spi1: flash-controller@1e630000 {
144 reg = < 0x1e630000 0xc4
145 0x30000000 0x08000000 >;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "aspeed,ast2600-spi";
149 clocks = <&scu ASPEED_CLK_AHB>;
150 num-cs = <2>;
151 status = "disabled";
152 flash@0 {
153 reg = < 0 >;
154 compatible = "jedec,spi-nor";
155 status = "disabled";
156 };
157 flash@1 {
158 reg = < 1 >;
159 compatible = "jedec,spi-nor";
160 status = "disabled";
161 };
162 };
163
164 spi2: flash-controller@1e631000 {
165 reg = < 0x1e631000 0xc4
166 0x50000000 0x08000000 >;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "aspeed,ast2600-spi";
170 clocks = <&scu ASPEED_CLK_AHB>;
171 num-cs = <3>;
172 status = "disabled";
173 flash@0 {
174 reg = < 0 >;
175 compatible = "jedec,spi-nor";
176 status = "disabled";
177 };
178 flash@1 {
179 reg = < 1 >;
180 compatible = "jedec,spi-nor";
181 status = "disabled";
182 };
183 flash@2 {
184 reg = < 2 >;
185 compatible = "jedec,spi-nor";
186 status = "disabled";
187 };
188 };
189
Joel Stanleyd18ef4f2021-10-27 14:17:28 +0800[diff] [blame]190 hace: hace@1e6d0000 {
191 compatible = "aspeed,ast2600-hace";
192 reg = <0x1e6d0000 0x200>;
193 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&scu ASPEED_CLK_GATE_YCLK>;
195 status = "disabled";
196 };
197
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]198 edac: sdram@1e6e0000 {
199 compatible = "aspeed,ast2600-sdram-edac";
200 reg = <0x1e6e0000 0x174>;
201 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
202 };
203
204 mdio: ethernet@1e650000 {
205 compatible = "aspeed,aspeed-mdio";
206 reg = <0x1e650000 0x40>;
207 resets = <&rst ASPEED_RESET_MII>;
208 status = "disabled";
209 };
210
211 mac0: ftgmac@1e660000 {
212 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
213 reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
214 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
216 status = "disabled";
217 };
218
219 mac1: ftgmac@1e680000 {
220 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
221 reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
226 status = "disabled";
227 };
228
229 mac2: ftgmac@1e670000 {
230 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
231 reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
232 #address-cells = <1>;
233 #size-cells = <0>;
234 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
236 status = "disabled";
237 };
238
239 mac3: ftgmac@1e690000 {
240 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
241 reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
242 #address-cells = <1>;
243 #size-cells = <0>;
244 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
246 status = "disabled";
247 };
248
249 ehci0: usb@1e6a1000 {
250 compatible = "aspeed,aspeed-ehci", "usb-ehci";
251 reg = <0x1e6a1000 0x100>;
252 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_usb2ah_default>;
256 status = "disabled";
257 };
258
259 ehci1: usb@1e6a3000 {
260 compatible = "aspeed,aspeed-ehci", "usb-ehci";
261 reg = <0x1e6a3000 0x100>;
262 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_usb2bh_default>;
266 status = "disabled";
267 };
268
269 apb {
270 compatible = "simple-bus";
271 #address-cells = <1>;
272 #size-cells = <1>;
273 ranges;
274
275 syscon: syscon@1e6e2000 {
276 compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
277 reg = <0x1e6e2000 0x1000>;
278 #address-cells = <1>;
279 #size-cells = <1>;
280 #clock-cells = <1>;
281 #reset-cells = <1>;
282 ranges = <0 0x1e6e2000 0x1000>;
283
284 pinctrl: pinctrl {
285 compatible = "aspeed,g6-pinctrl";
286 aspeed,external-nodes = <&gfx &lhc>;
287
288 };
289
290 vga_scratch: scratch {
291 compatible = "aspeed,bmc-misc";
292 };
293
294 scu_ic0: interrupt-controller@0 {
295 #interrupt-cells = <1>;
296 compatible = "aspeed,ast2600-scu-ic";
297 reg = <0x560 0x10>;
298 interrupt-parent = <&gic>;
299 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
300 interrupt-controller;
301 };
302
303 scu_ic1: interrupt-controller@1 {
304 #interrupt-cells = <1>;
305 compatible = "aspeed,ast2600-scu-ic";
306 reg = <0x570 0x10>;
307 interrupt-parent = <&gic>;
308 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-controller;
310 };
311
312 };
313
314 smp-memram@0 {
315 compatible = "aspeed,ast2600-smpmem", "syscon";
316 reg = <0x1e6e2180 0x40>;
317 };
318
319 gfx: display@1e6e6000 {
320 compatible = "aspeed,ast2500-gfx", "syscon";
321 reg = <0x1e6e6000 0x1000>;
322 reg-io-width = <4>;
323 };
324
325 pcie_bridge0: pcie@1e6ed000 {
326 compatible = "aspeed,ast2600-pcie";
327 #address-cells = <3>;
328 #size-cells = <2>;
329 reg = <0x1e6ed000 0x100>;
330 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000>,
331 <0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>;
332 device_type = "pci";
333 bus-range = <0x00 0xff>;
334 resets = <&rst ASPEED_RESET_PCIE_DEV_O>;
335 cfg-handle = <&pcie_cfg0>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_pcie0rc_default>;
338
339 status = "disabled";
340 };
341
342 pcie_bridge1: pcie@1e6ed200 {
343 compatible = "aspeed,ast2600-pcie";
344 #address-cells = <3>;
345 #size-cells = <2>;
346 reg = <0x1e6ed200 0x100>;
347 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000>,
348 <0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
349 device_type = "pci";
350 bus-range = <0x00 0xff>;
351 resets = <&rst ASPEED_RESET_PCIE_RC_O>;
352 cfg-handle = <&pcie_cfg1>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_pcie1rc_default>;
355
356 status = "disabled";
357 };
358
359 sdhci: sdhci@1e740000 {
360 #interrupt-cells = <1>;
361 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
362 reg = <0x1e740000 0x1000>;
363 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
364 interrupt-controller;
365 clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
366 <&scu ASPEED_CLK_GATE_SDEXTCLK>;
367 clock-names = "ctrlclk", "extclk";
368 #address-cells = <1>;
369 #size-cells = <1>;
370 ranges = <0x0 0x1e740000 0x1000>;
371
372 sdhci_slot0: sdhci_slot0@100 {
373 compatible = "aspeed,sdhci-ast2600";
374 reg = <0x100 0x100>;
375 interrupts = <0>;
376 interrupt-parent = <&sdhci>;
377 sdhci,auto-cmd12;
378 clocks = <&scu ASPEED_CLK_SDIO>;
379 status = "disabled";
380 };
381
382 sdhci_slot1: sdhci_slot1@200 {
383 compatible = "aspeed,sdhci-ast2600";
384 reg = <0x200 0x100>;
385 interrupts = <1>;
386 interrupt-parent = <&sdhci>;
387 sdhci,auto-cmd12;
388 clocks = <&scu ASPEED_CLK_SDIO>;
389 status = "disabled";
390 };
391 };
392
393 emmc: emmc@1e750000 {
394 #interrupt-cells = <1>;
395 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
396 reg = <0x1e750000 0x1000>;
397 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
398 interrupt-controller;
399 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
400 <&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
401 clock-names = "ctrlclk", "extclk";
402 #address-cells = <1>;
403 #size-cells = <1>;
404 ranges = <0x0 0x1e750000 0x1000>;
405
406 emmc_slot0: emmc_slot0@100 {
407 compatible = "aspeed,emmc-ast2600";
408 reg = <0x100 0x100>;
409 interrupts = <0>;
410 interrupt-parent = <&emmc>;
411 clocks = <&scu ASPEED_CLK_EMMC>;
412 status = "disabled";
413 };
414 };
415
416 h2x: h2x@1e770000 {
417 compatible = "aspeed,ast2600-h2x";
418 reg = <0x1e770000 0x100>;
419 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
420 resets = <&rst ASPEED_RESET_H2X>;
421 #address-cells = <1>;
422 #size-cells = <1>;
423 ranges = <0x0 0x1e770000 0x100>;
424
425 status = "disabled";
426
427 pcie_cfg0: cfg0@80 {
428 reg = <0x80 0x80>;
429 compatible = "aspeed,ast2600-pcie-cfg";
430 };
431
432 pcie_cfg1: cfg1@C0 {
433 compatible = "aspeed,ast2600-pcie-cfg";
434 reg = <0xC0 0x80>;
435 };
436 };
437
438 gpio0: gpio@1e780000 {
439 compatible = "aspeed,ast2600-gpio";
440 reg = <0x1e780000 0x1000>;
441 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
442 #gpio-cells = <2>;
443 gpio-controller;
444 interrupt-controller;
445 gpio-ranges = <&pinctrl 0 0 220>;
446 ngpios = <208>;
447 };
448
449 gpio1: gpio@1e780800 {
450 compatible = "aspeed,ast2600-gpio";
451 reg = <0x1e780800 0x800>;
452 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
453 #gpio-cells = <2>;
454 gpio-controller;
455 interrupt-controller;
456 gpio-ranges = <&pinctrl 0 0 208>;
457 ngpios = <36>;
458 };
459
460 uart1: serial@1e783000 {
461 compatible = "ns16550a";
462 reg = <0x1e783000 0x20>;
463 reg-shift = <2>;
464 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
466 clock-frequency = <1846154>;
467 no-loopback-test;
468 status = "disabled";
469 };
470
471 uart5: serial@1e784000 {
472 compatible = "ns16550a";
473 reg = <0x1e784000 0x1000>;
474 reg-shift = <2>;
475 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
477 clock-frequency = <1846154>;
478 no-loopback-test;
479 status = "disabled";
480 };
481
482 wdt1: watchdog@1e785000 {
483 compatible = "aspeed,ast2600-wdt";
484 reg = <0x1e785000 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]485 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]486 };
487
488 wdt2: watchdog@1e785040 {
489 compatible = "aspeed,ast2600-wdt";
490 reg = <0x1e785040 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]491 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]492 };
493
494 wdt3: watchdog@1e785080 {
495 compatible = "aspeed,ast2600-wdt";
496 reg = <0x1e785080 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]497 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]498 };
499
500 wdt4: watchdog@1e7850C0 {
501 compatible = "aspeed,ast2600-wdt";
502 reg = <0x1e7850C0 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]503 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]504 };
505
506 lpc: lpc@1e789000 {
507 compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
508 reg = <0x1e789000 0x1000>;
509
510 #address-cells = <1>;
511 #size-cells = <1>;
512 ranges = <0x0 0x1e789000 0x1000>;
513
514 kcs1: kcs1@0 {
515 compatible = "aspeed,ast2600-kcs-bmc";
516 reg = <0x0 0x80>;
517 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
518 kcs_chan = <1>;
519 kcs_addr = <0xCA0>;
520 status = "disabled";
521 };
522
523 kcs2: kcs2@0 {
524 compatible = "aspeed,ast2600-kcs-bmc";
525 reg = <0x0 0x80>;
526 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
527 kcs_chan = <2>;
528 kcs_addr = <0xCA8>;
529 status = "disabled";
530 };
531
532 kcs3: kcs3@0 {
533 compatible = "aspeed,ast2600-kcs-bmc";
534 reg = <0x0 0x80>;
535 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
536 kcs_chan = <3>;
537 kcs_addr = <0xCA2>;
538 };
539
540 kcs4: kcs4@0 {
541 compatible = "aspeed,ast2600-kcs-bmc";
542 reg = <0x0 0x120>;
543 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
544 kcs_chan = <4>;
545 kcs_addr = <0xCA4>;
546 status = "disabled";
547 };
548
549 lpc_ctrl: lpc-ctrl@80 {
550 compatible = "aspeed,ast2600-lpc-ctrl";
551 reg = <0x80 0x80>;
552 status = "disabled";
553 };
554
555 lpc_snoop: lpc-snoop@80 {
556 compatible = "aspeed,ast2600-lpc-snoop";
557 reg = <0x80 0x80>;
558 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
559 status = "disabled";
560 };
561
562 lhc: lhc@a0 {
563 compatible = "aspeed,ast2600-lhc";
564 reg = <0xa0 0x24 0xc8 0x8>;
565 };
566
567 lpc_reset: reset-controller@98 {
568 compatible = "aspeed,ast2600-lpc-reset";
569 reg = <0x98 0x4>;
570 #reset-cells = <1>;
571 status = "disabled";
572 };
573
574 ibt: ibt@140 {
575 compatible = "aspeed,ast2600-ibt-bmc";
576 reg = <0x140 0x18>;
577 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
578 status = "disabled";
579 };
580
581 sio_regs: regs {
582 compatible = "aspeed,bmc-misc";
583 };
584
585 mbox: mbox@200 {
586 compatible = "aspeed,ast2600-mbox";
587 reg = <0x200 0x5c>;
588 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
589 #mbox-cells = <1>;
590 status = "disabled";
591 };
592 };
593
594 uart2: serial@1e78d000 {
595 compatible = "ns16550a";
596 reg = <0x1e78d000 0x20>;
597 reg-shift = <2>;
598 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
600 clock-frequency = <1846154>;
601 no-loopback-test;
602 status = "disabled";
603 };
604
605 uart3: serial@1e78e000 {
606 compatible = "ns16550a";
607 reg = <0x1e78e000 0x20>;
608 reg-shift = <2>;
609 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
611 clock-frequency = <1846154>;
612 no-loopback-test;
613 status = "disabled";
614 };
615
616 uart4: serial@1e78f000 {
617 compatible = "ns16550a";
618 reg = <0x1e78f000 0x20>;
619 reg-shift = <2>;
620 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
622 clock-frequency = <1846154>;
623 no-loopback-test;
624 status = "disabled";
625 };
626
627 i2c: bus@1e78a000 {
628 compatible = "simple-bus";
629 #address-cells = <1>;
630 #size-cells = <1>;
631 ranges = <0 0x1e78a000 0x1000>;
632 };
633
634 fsim0: fsi@1e79b000 {
635 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
636 reg = <0x1e79b000 0x94>;
637 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&pinctrl_fsi1_default>;
640 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
641 status = "disabled";
642 };
643
644 fsim1: fsi@1e79b100 {
645 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
646 reg = <0x1e79b100 0x94>;
647 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_fsi2_default>;
650 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
651 status = "disabled";
652 };
653
654 uart6: serial@1e790000 {
655 compatible = "ns16550a";
656 reg = <0x1e790000 0x20>;
657 reg-shift = <2>;
658 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
660 clock-frequency = <1846154>;
661 no-loopback-test;
662 status = "disabled";
663 };
664
665 uart7: serial@1e790100 {
666 compatible = "ns16550a";
667 reg = <0x1e790100 0x20>;
668 reg-shift = <2>;
669 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
671 clock-frequency = <1846154>;
672 no-loopback-test;
673 status = "disabled";
674 };
675
676 uart8: serial@1e790200 {
677 compatible = "ns16550a";
678 reg = <0x1e790200 0x20>;
679 reg-shift = <2>;
680 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
682 clock-frequency = <1846154>;
683 no-loopback-test;
684 status = "disabled";
685 };
686
687 uart9: serial@1e790300 {
688 compatible = "ns16550a";
689 reg = <0x1e790300 0x20>;
690 reg-shift = <2>;
691 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
693 clock-frequency = <1846154>;
694 no-loopback-test;
695 status = "disabled";
696 };
697
698 uart10: serial@1e790400 {
699 compatible = "ns16550a";
700 reg = <0x1e790400 0x20>;
701 reg-shift = <2>;
702 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
704 clock-frequency = <1846154>;
705 no-loopback-test;
706 status = "disabled";
707 };
708
709 uart11: serial@1e790500 {
710 compatible = "ns16550a";
711 reg = <0x1e790400 0x20>;
712 reg-shift = <2>;
713 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
715 clock-frequency = <1846154>;
716 no-loopback-test;
717 status = "disabled";
718 };
719
720 uart12: serial@1e790600 {
721 compatible = "ns16550a";
722 reg = <0x1e790600 0x20>;
723 reg-shift = <2>;
724 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
726 clock-frequency = <1846154>;
727 no-loopback-test;
728 status = "disabled";
729 };
730
731 uart13: serial@1e790700 {
732 compatible = "ns16550a";
733 reg = <0x1e790700 0x20>;
734 reg-shift = <2>;
735 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
737 clock-frequency = <1846154>;
738 no-loopback-test;
739 status = "disabled";
740 };
741
742 display_port: dp@1e6eb000 {
743 compatible = "aspeed,ast2600-displayport";
744 reg = <0x1e6eb000 0x200>;
745 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
746 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>;
747 status = "disabled";
748 };
749
750 };
751
752 };
753
754};
755
756&i2c {
757 i2cglobal: i2cg@00 {
758 compatible = "aspeed,ast2600-i2c-global";
759 reg = <0x0 0x40>;
760 resets = <&rst ASPEED_RESET_I2C>;
761#if 0
762 new-mode;
763#endif
764 };
765
766 i2c0: i2c@80 {
767 #address-cells = <1>;
768 #size-cells = <0>;
769 #interrupt-cells = <1>;
770
771 reg = <0x80 0x80 0xC00 0x20>;
772 compatible = "aspeed,ast2600-i2c-bus";
773 bus-frequency = <100000>;
774 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&scu ASPEED_CLK_APB2>;
776 status = "disabled";
777 };
778
779 i2c1: i2c@100 {
780 #address-cells = <1>;
781 #size-cells = <0>;
782 #interrupt-cells = <1>;
783
784 reg = <0x100 0x80 0xC20 0x20>;
785 compatible = "aspeed,ast2600-i2c-bus";
786 bus-frequency = <100000>;
787 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&scu ASPEED_CLK_APB2>;
789 status = "disabled";
790 };
791
792 i2c2: i2c@180 {
793 #address-cells = <1>;
794 #size-cells = <0>;
795 #interrupt-cells = <1>;
796
797 reg = <0x180 0x80 0xC40 0x20>;
798 compatible = "aspeed,ast2600-i2c-bus";
799 bus-frequency = <100000>;
800 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&scu ASPEED_CLK_APB2>;
802 };
803
804 i2c3: i2c@200 {
805 #address-cells = <1>;
806 #size-cells = <0>;
807 #interrupt-cells = <1>;
808
809 reg = <0x200 0x40 0xC60 0x20>;
810 compatible = "aspeed,ast2600-i2c-bus";
811 bus-frequency = <100000>;
812 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&scu ASPEED_CLK_APB2>;
814 };
815
816 i2c4: i2c@280 {
817 #address-cells = <1>;
818 #size-cells = <0>;
819 #interrupt-cells = <1>;
820
821 reg = <0x280 0x80 0xC80 0x20>;
822 compatible = "aspeed,ast2600-i2c-bus";
823 bus-frequency = <100000>;
824 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&scu ASPEED_CLK_APB2>;
826 };
827
828 i2c5: i2c@300 {
829 #address-cells = <1>;
830 #size-cells = <0>;
831 #interrupt-cells = <1>;
832
833 reg = <0x300 0x40 0xCA0 0x20>;
834 compatible = "aspeed,ast2600-i2c-bus";
835 bus-frequency = <100000>;
836 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&scu ASPEED_CLK_APB2>;
838 };
839
840 i2c6: i2c@380 {
841 #address-cells = <1>;
842 #size-cells = <0>;
843 #interrupt-cells = <1>;
844
845 reg = <0x380 0x80 0xCC0 0x20>;
846 compatible = "aspeed,ast2600-i2c-bus";
847 bus-frequency = <100000>;
848 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&scu ASPEED_CLK_APB2>;
850 };
851
852 i2c7: i2c@400 {
853 #address-cells = <1>;
854 #size-cells = <0>;
855 #interrupt-cells = <1>;
856
857 reg = <0x400 0x80 0xCE0 0x20>;
858 compatible = "aspeed,ast2600-i2c-bus";
859 bus-frequency = <100000>;
860 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&scu ASPEED_CLK_APB2>;
862 };
863
864 i2c8: i2c@480 {
865 #address-cells = <1>;
866 #size-cells = <0>;
867 #interrupt-cells = <1>;
868
869 reg = <0x480 0x80 0xD00 0x20>;
870 compatible = "aspeed,ast2600-i2c-bus";
871 bus-frequency = <100000>;
872 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&scu ASPEED_CLK_APB2>;
874 };
875
876 i2c9: i2c@500 {
877 #address-cells = <1>;
878 #size-cells = <0>;
879 #interrupt-cells = <1>;
880
881 reg = <0x500 0x80 0xD20 0x20>;
882 compatible = "aspeed,ast2600-i2c-bus";
883 bus-frequency = <100000>;
884 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&scu ASPEED_CLK_APB2>;
886 status = "disabled";
887 };
888
889 i2c10: i2c@580 {
890 #address-cells = <1>;
891 #size-cells = <0>;
892 #interrupt-cells = <1>;
893
894 reg = <0x580 0x80 0xD40 0x20>;
895 compatible = "aspeed,ast2600-i2c-bus";
896 bus-frequency = <100000>;
897 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&scu ASPEED_CLK_APB2>;
899 status = "disabled";
900 };
901
902 i2c11: i2c@600 {
903 #address-cells = <1>;
904 #size-cells = <0>;
905 #interrupt-cells = <1>;
906
907 reg = <0x600 0x80 0xD60 0x20>;
908 compatible = "aspeed,ast2600-i2c-bus";
909 bus-frequency = <100000>;
910 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&scu ASPEED_CLK_APB2>;
912 status = "disabled";
913 };
914
915 i2c12: i2c@680 {
916 #address-cells = <1>;
917 #size-cells = <0>;
918 #interrupt-cells = <1>;
919
920 reg = <0x680 0x80 0xD80 0x20>;
921 compatible = "aspeed,ast2600-i2c-bus";
922 bus-frequency = <100000>;
923 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&scu ASPEED_CLK_APB2>;
925 status = "disabled";
926 };
927
928 i2c13: i2c@700 {
929 #address-cells = <1>;
930 #size-cells = <0>;
931 #interrupt-cells = <1>;
932
933 reg = <0x700 0x80 0xDA0 0x20>;
934 compatible = "aspeed,ast2600-i2c-bus";
935 bus-frequency = <100000>;
936 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&scu ASPEED_CLK_APB2>;
938 status = "disabled";
939 };
940
941 i2c14: i2c@780 {
942 #address-cells = <1>;
943 #size-cells = <0>;
944 #interrupt-cells = <1>;
945
946 reg = <0x780 0x80 0xDC0 0x20>;
947 compatible = "aspeed,ast2600-i2c-bus";
948 bus-frequency = <100000>;
949 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&scu ASPEED_CLK_APB2>;
951 status = "disabled";
952 };
953
954 i2c15: i2c@800 {
955 #address-cells = <1>;
956 #size-cells = <0>;
957 #interrupt-cells = <1>;
958
959 reg = <0x800 0x80 0xDE0 0x20>;
960 compatible = "aspeed,ast2600-i2c-bus";
961 bus-frequency = <100000>;
962 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&scu ASPEED_CLK_APB2>;
964 status = "disabled";
965 };
966
967};
968
969&pinctrl {
970 pinctrl_fmcquad_default: fmcquad_default {
971 function = "FMCQUAD";
972 groups = "FMCQUAD";
973 };
974
975 pinctrl_spi1_default: spi1_default {
976 function = "SPI1";
977 groups = "SPI1";
978 };
979
980 pinctrl_spi1abr_default: spi1abr_default {
981 function = "SPI1ABR";
982 groups = "SPI1ABR";
983 };
984
985 pinctrl_spi1cs1_default: spi1cs1_default {
986 function = "SPI1CS1";
987 groups = "SPI1CS1";
988 };
989
990 pinctrl_spi1wp_default: spi1wp_default {
991 function = "SPI1WP";
992 groups = "SPI1WP";
993 };
994
995 pinctrl_spi1quad_default: spi1quad_default {
996 function = "SPI1QUAD";
997 groups = "SPI1QUAD";
998 };
999
1000 pinctrl_spi2_default: spi2_default {
1001 function = "SPI2";
1002 groups = "SPI2";
1003 };
1004
1005 pinctrl_spi2cs1_default: spi2cs1_default {
1006 function = "SPI2CS1";
1007 groups = "SPI2CS1";
1008 };
1009
1010 pinctrl_spi2cs2_default: spi2cs2_default {
1011 function = "SPI2CS2";
1012 groups = "SPI2CS2";
1013 };
1014
1015 pinctrl_spi2quad_default: spi2quad_default {
1016 function = "SPI2QUAD";
1017 groups = "SPI2QUAD";
1018 };
1019
1020 pinctrl_acpi_default: acpi_default {
1021 function = "ACPI";
1022 groups = "ACPI";
1023 };
1024
1025 pinctrl_adc0_default: adc0_default {
1026 function = "ADC0";
1027 groups = "ADC0";
1028 };
1029
1030 pinctrl_adc1_default: adc1_default {
1031 function = "ADC1";
1032 groups = "ADC1";
1033 };
1034
1035 pinctrl_adc10_default: adc10_default {
1036 function = "ADC10";
1037 groups = "ADC10";
1038 };
1039
1040 pinctrl_adc11_default: adc11_default {
1041 function = "ADC11";
1042 groups = "ADC11";
1043 };
1044
1045 pinctrl_adc12_default: adc12_default {
1046 function = "ADC12";
1047 groups = "ADC12";
1048 };
1049
1050 pinctrl_adc13_default: adc13_default {
1051 function = "ADC13";
1052 groups = "ADC13";
1053 };
1054
1055 pinctrl_adc14_default: adc14_default {
1056 function = "ADC14";
1057 groups = "ADC14";
1058 };
1059
1060 pinctrl_adc15_default: adc15_default {
1061 function = "ADC15";
1062 groups = "ADC15";
1063 };
1064
1065 pinctrl_adc2_default: adc2_default {
1066 function = "ADC2";
1067 groups = "ADC2";
1068 };
1069
1070 pinctrl_adc3_default: adc3_default {
1071 function = "ADC3";
1072 groups = "ADC3";
1073 };
1074
1075 pinctrl_adc4_default: adc4_default {
1076 function = "ADC4";
1077 groups = "ADC4";
1078 };
1079
1080 pinctrl_adc5_default: adc5_default {
1081 function = "ADC5";
1082 groups = "ADC5";
1083 };
1084
1085 pinctrl_adc6_default: adc6_default {
1086 function = "ADC6";
1087 groups = "ADC6";
1088 };
1089
1090 pinctrl_adc7_default: adc7_default {
1091 function = "ADC7";
1092 groups = "ADC7";
1093 };
1094
1095 pinctrl_adc8_default: adc8_default {
1096 function = "ADC8";
1097 groups = "ADC8";
1098 };
1099
1100 pinctrl_adc9_default: adc9_default {
1101 function = "ADC9";
1102 groups = "ADC9";
1103 };
1104
1105 pinctrl_bmcint_default: bmcint_default {
1106 function = "BMCINT";
1107 groups = "BMCINT";
1108 };
1109
1110 pinctrl_ddcclk_default: ddcclk_default {
1111 function = "DDCCLK";
1112 groups = "DDCCLK";
1113 };
1114
1115 pinctrl_ddcdat_default: ddcdat_default {
1116 function = "DDCDAT";
1117 groups = "DDCDAT";
1118 };
1119
1120 pinctrl_espi_default: espi_default {
1121 function = "ESPI";
1122 groups = "ESPI";
1123 };
1124
1125 pinctrl_fsi1_default: fsi1_default {
1126 function = "FSI1";
1127 groups = "FSI1";
1128 };
1129
1130 pinctrl_fsi2_default: fsi2_default {
1131 function = "FSI2";
1132 groups = "FSI2";
1133 };
1134
1135 pinctrl_fwspics1_default: fwspics1_default {
1136 function = "FWSPICS1";
1137 groups = "FWSPICS1";
1138 };
1139
1140 pinctrl_fwspics2_default: fwspics2_default {
1141 function = "FWSPICS2";
1142 groups = "FWSPICS2";
1143 };
1144
1145 pinctrl_gpid0_default: gpid0_default {
1146 function = "GPID0";
1147 groups = "GPID0";
1148 };
1149
1150 pinctrl_gpid2_default: gpid2_default {
1151 function = "GPID2";
1152 groups = "GPID2";
1153 };
1154
1155 pinctrl_gpid4_default: gpid4_default {
1156 function = "GPID4";
1157 groups = "GPID4";
1158 };
1159
1160 pinctrl_gpid6_default: gpid6_default {
1161 function = "GPID6";
1162 groups = "GPID6";
1163 };
1164
1165 pinctrl_gpie0_default: gpie0_default {
1166 function = "GPIE0";
1167 groups = "GPIE0";
1168 };
1169
1170 pinctrl_gpie2_default: gpie2_default {
1171 function = "GPIE2";
1172 groups = "GPIE2";
1173 };
1174
1175 pinctrl_gpie4_default: gpie4_default {
1176 function = "GPIE4";
1177 groups = "GPIE4";
1178 };
1179
1180 pinctrl_gpie6_default: gpie6_default {
1181 function = "GPIE6";
1182 groups = "GPIE6";
1183 };
1184
1185 pinctrl_i2c1_default: i2c1_default {
1186 function = "I2C1";
1187 groups = "I2C1";
1188 };
1189 pinctrl_i2c2_default: i2c2_default {
1190 function = "I2C2";
1191 groups = "I2C2";
1192 };
1193
1194 pinctrl_i2c3_default: i2c3_default {
1195 function = "I2C3";
1196 groups = "I2C3";
1197 };
1198
1199 pinctrl_i2c4_default: i2c4_default {
1200 function = "I2C4";
1201 groups = "I2C4";
1202 };
1203
1204 pinctrl_i2c5_default: i2c5_default {
1205 function = "I2C5";
1206 groups = "I2C5";
1207 };
1208
1209 pinctrl_i2c6_default: i2c6_default {
1210 function = "I2C6";
1211 groups = "I2C6";
1212 };
1213
1214 pinctrl_i2c7_default: i2c7_default {
1215 function = "I2C7";
1216 groups = "I2C7";
1217 };
1218
1219 pinctrl_i2c8_default: i2c8_default {
1220 function = "I2C8";
1221 groups = "I2C8";
1222 };
1223
1224 pinctrl_i2c9_default: i2c9_default {
1225 function = "I2C9";
1226 groups = "I2C9";
1227 };
1228
1229 pinctrl_i2c10_default: i2c10_default {
1230 function = "I2C10";
1231 groups = "I2C10";
1232 };
1233
1234 pinctrl_i2c11_default: i2c11_default {
1235 function = "I2C11";
1236 groups = "I2C11";
1237 };
1238
1239 pinctrl_i2c12_default: i2c12_default {
1240 function = "I2C12";
1241 groups = "I2C12";
1242 };
1243
1244 pinctrl_i2c13_default: i2c13_default {
1245 function = "I2C13";
1246 groups = "I2C13";
1247 };
1248
1249 pinctrl_i2c14_default: i2c14_default {
1250 function = "I2C14";
1251 groups = "I2C14";
1252 };
1253
1254 pinctrl_i2c15_default: i2c15_default {
1255 function = "I2C15";
1256 groups = "I2C15";
1257 };
1258
1259 pinctrl_i2c16_default: i2c16_default {
1260 function = "I2C16";
1261 groups = "I2C16";
1262 };
1263
1264 pinctrl_lad0_default: lad0_default {
1265 function = "LAD0";
1266 groups = "LAD0";
1267 };
1268
1269 pinctrl_lad1_default: lad1_default {
1270 function = "LAD1";
1271 groups = "LAD1";
1272 };
1273
1274 pinctrl_lad2_default: lad2_default {
1275 function = "LAD2";
1276 groups = "LAD2";
1277 };
1278
1279 pinctrl_lad3_default: lad3_default {
1280 function = "LAD3";
1281 groups = "LAD3";
1282 };
1283
1284 pinctrl_lclk_default: lclk_default {
1285 function = "LCLK";
1286 groups = "LCLK";
1287 };
1288
1289 pinctrl_lframe_default: lframe_default {
1290 function = "LFRAME";
1291 groups = "LFRAME";
1292 };
1293
1294 pinctrl_lpchc_default: lpchc_default {
1295 function = "LPCHC";
1296 groups = "LPCHC";
1297 };
1298
1299 pinctrl_lpcpd_default: lpcpd_default {
1300 function = "LPCPD";
1301 groups = "LPCPD";
1302 };
1303
1304 pinctrl_lpcplus_default: lpcplus_default {
1305 function = "LPCPLUS";
1306 groups = "LPCPLUS";
1307 };
1308
1309 pinctrl_lpcpme_default: lpcpme_default {
1310 function = "LPCPME";
1311 groups = "LPCPME";
1312 };
1313
1314 pinctrl_lpcrst_default: lpcrst_default {
1315 function = "LPCRST";
1316 groups = "LPCRST";
1317 };
1318
1319 pinctrl_lpcsmi_default: lpcsmi_default {
1320 function = "LPCSMI";
1321 groups = "LPCSMI";
1322 };
1323
1324 pinctrl_lsirq_default: lsirq_default {
1325 function = "LSIRQ";
1326 groups = "LSIRQ";
1327 };
1328
1329 pinctrl_mac1link_default: mac1link_default {
1330 function = "MAC1LINK";
1331 groups = "MAC1LINK";
1332 };
1333
1334 pinctrl_mac2link_default: mac2link_default {
1335 function = "MAC2LINK";
1336 groups = "MAC2LINK";
1337 };
1338
1339 pinctrl_mac3link_default: mac3link_default {
1340 function = "MAC3LINK";
1341 groups = "MAC3LINK";
1342 };
1343
1344 pinctrl_mac4link_default: mac4link_default {
1345 function = "MAC4LINK";
1346 groups = "MAC4LINK";
1347 };
1348
1349 pinctrl_mdio1_default: mdio1_default {
1350 function = "MDIO1";
1351 groups = "MDIO1";
1352 };
1353
1354 pinctrl_mdio2_default: mdio2_default {
1355 function = "MDIO2";
1356 groups = "MDIO2";
1357 };
1358
1359 pinctrl_mdio3_default: mdio3_default {
1360 function = "MDIO3";
1361 groups = "MDIO3";
1362 };
1363
1364 pinctrl_mdio4_default: mdio4_default {
1365 function = "MDIO4";
1366 groups = "MDIO4";
1367 };
1368
1369 pinctrl_rmii1_default: rmii1_default {
1370 function = "RMII1";
1371 groups = "RMII1";
1372 };
1373
1374 pinctrl_rmii2_default: rmii2_default {
1375 function = "RMII2";
1376 groups = "RMII2";
1377 };
1378
1379 pinctrl_rmii3_default: rmii3_default {
1380 function = "RMII3";
1381 groups = "RMII3";
1382 };
1383
1384 pinctrl_rmii4_default: rmii4_default {
1385 function = "RMII4";
1386 groups = "RMII4";
1387 };
1388
1389 pinctrl_rmii1rclk_default: rmii1rclk_default {
1390 function = "RMII1RCLK";
1391 groups = "RMII1RCLK";
1392 };
1393
1394 pinctrl_rmii2rclk_default: rmii2rclk_default {
1395 function = "RMII2RCLK";
1396 groups = "RMII2RCLK";
1397 };
1398
1399 pinctrl_rmii3rclk_default: rmii3rclk_default {
1400 function = "RMII3RCLK";
1401 groups = "RMII3RCLK";
1402 };
1403
1404 pinctrl_rmii4rclk_default: rmii4rclk_default {
1405 function = "RMII4RCLK";
1406 groups = "RMII4RCLK";
1407 };
1408
1409 pinctrl_ncts1_default: ncts1_default {
1410 function = "NCTS1";
1411 groups = "NCTS1";
1412 };
1413
1414 pinctrl_ncts2_default: ncts2_default {
1415 function = "NCTS2";
1416 groups = "NCTS2";
1417 };
1418
1419 pinctrl_ncts3_default: ncts3_default {
1420 function = "NCTS3";
1421 groups = "NCTS3";
1422 };
1423
1424 pinctrl_ncts4_default: ncts4_default {
1425 function = "NCTS4";
1426 groups = "NCTS4";
1427 };
1428
1429 pinctrl_ndcd1_default: ndcd1_default {
1430 function = "NDCD1";
1431 groups = "NDCD1";
1432 };
1433
1434 pinctrl_ndcd2_default: ndcd2_default {
1435 function = "NDCD2";
1436 groups = "NDCD2";
1437 };
1438
1439 pinctrl_ndcd3_default: ndcd3_default {
1440 function = "NDCD3";
1441 groups = "NDCD3";
1442 };
1443
1444 pinctrl_ndcd4_default: ndcd4_default {
1445 function = "NDCD4";
1446 groups = "NDCD4";
1447 };
1448
1449 pinctrl_ndsr1_default: ndsr1_default {
1450 function = "NDSR1";
1451 groups = "NDSR1";
1452 };
1453
1454 pinctrl_ndsr2_default: ndsr2_default {
1455 function = "NDSR2";
1456 groups = "NDSR2";
1457 };
1458
1459 pinctrl_ndsr3_default: ndsr3_default {
1460 function = "NDSR3";
1461 groups = "NDSR3";
1462 };
1463
1464 pinctrl_ndsr4_default: ndsr4_default {
1465 function = "NDSR4";
1466 groups = "NDSR4";
1467 };
1468
1469 pinctrl_ndtr1_default: ndtr1_default {
1470 function = "NDTR1";
1471 groups = "NDTR1";
1472 };
1473
1474 pinctrl_ndtr2_default: ndtr2_default {
1475 function = "NDTR2";
1476 groups = "NDTR2";
1477 };
1478
1479 pinctrl_ndtr3_default: ndtr3_default {
1480 function = "NDTR3";
1481 groups = "NDTR3";
1482 };
1483
1484 pinctrl_ndtr4_default: ndtr4_default {
1485 function = "NDTR4";
1486 groups = "NDTR4";
1487 };
1488
1489 pinctrl_nri1_default: nri1_default {
1490 function = "NRI1";
1491 groups = "NRI1";
1492 };
1493
1494 pinctrl_nri2_default: nri2_default {
1495 function = "NRI2";
1496 groups = "NRI2";
1497 };
1498
1499 pinctrl_nri3_default: nri3_default {
1500 function = "NRI3";
1501 groups = "NRI3";
1502 };
1503
1504 pinctrl_nri4_default: nri4_default {
1505 function = "NRI4";
1506 groups = "NRI4";
1507 };
1508
1509 pinctrl_nrts1_default: nrts1_default {
1510 function = "NRTS1";
1511 groups = "NRTS1";
1512 };
1513
1514 pinctrl_nrts2_default: nrts2_default {
1515 function = "NRTS2";
1516 groups = "NRTS2";
1517 };
1518
1519 pinctrl_nrts3_default: nrts3_default {
1520 function = "NRTS3";
1521 groups = "NRTS3";
1522 };
1523
1524 pinctrl_nrts4_default: nrts4_default {
1525 function = "NRTS4";
1526 groups = "NRTS4";
1527 };
1528
1529 pinctrl_oscclk_default: oscclk_default {
1530 function = "OSCCLK";
1531 groups = "OSCCLK";
1532 };
1533
1534 pinctrl_pewake_default: pewake_default {
1535 function = "PEWAKE";
1536 groups = "PEWAKE";
1537 };
1538
1539 pinctrl_pnor_default: pnor_default {
1540 function = "PNOR";
1541 groups = "PNOR";
1542 };
1543
1544 pinctrl_pwm0_default: pwm0_default {
1545 function = "PWM0";
1546 groups = "PWM0";
1547 };
1548
1549 pinctrl_pwm1_default: pwm1_default {
1550 function = "PWM1";
1551 groups = "PWM1";
1552 };
1553
1554 pinctrl_pwm2_default: pwm2_default {
1555 function = "PWM2";
1556 groups = "PWM2";
1557 };
1558
1559 pinctrl_pwm3_default: pwm3_default {
1560 function = "PWM3";
1561 groups = "PWM3";
1562 };
1563
1564 pinctrl_pwm4_default: pwm4_default {
1565 function = "PWM4";
1566 groups = "PWM4";
1567 };
1568
1569 pinctrl_pwm5_default: pwm5_default {
1570 function = "PWM5";
1571 groups = "PWM5";
1572 };
1573
1574 pinctrl_pwm6_default: pwm6_default {
1575 function = "PWM6";
1576 groups = "PWM6";
1577 };
1578
1579 pinctrl_pwm7_default: pwm7_default {
1580 function = "PWM7";
1581 groups = "PWM7";
1582 };
1583
1584 pinctrl_rgmii1_default: rgmii1_default {
1585 function = "RGMII1";
1586 groups = "RGMII1";
1587 };
1588
1589 pinctrl_rgmii2_default: rgmii2_default {
1590 function = "RGMII2";
1591 groups = "RGMII2";
1592 };
1593
1594 pinctrl_rgmii3_default: rgmii3_default {
1595 function = "RGMII3";
1596 groups = "RGMII3";
1597 };
1598
1599 pinctrl_rgmii4_default: rgmii4_default {
1600 function = "RGMII4";
1601 groups = "RGMII4";
1602 };
1603
1604 pinctrl_rmii1_default: rmii1_default {
1605 function = "RMII1";
1606 groups = "RMII1";
1607 };
1608
1609 pinctrl_rmii2_default: rmii2_default {
1610 function = "RMII2";
1611 groups = "RMII2";
1612 };
1613
1614 pinctrl_rxd1_default: rxd1_default {
1615 function = "RXD1";
1616 groups = "RXD1";
1617 };
1618
1619 pinctrl_rxd2_default: rxd2_default {
1620 function = "RXD2";
1621 groups = "RXD2";
1622 };
1623
1624 pinctrl_rxd3_default: rxd3_default {
1625 function = "RXD3";
1626 groups = "RXD3";
1627 };
1628
1629 pinctrl_rxd4_default: rxd4_default {
1630 function = "RXD4";
1631 groups = "RXD4";
1632 };
1633
1634 pinctrl_salt1_default: salt1_default {
1635 function = "SALT1";
1636 groups = "SALT1";
1637 };
1638
1639 pinctrl_salt10_default: salt10_default {
1640 function = "SALT10";
1641 groups = "SALT10";
1642 };
1643
1644 pinctrl_salt11_default: salt11_default {
1645 function = "SALT11";
1646 groups = "SALT11";
1647 };
1648
1649 pinctrl_salt12_default: salt12_default {
1650 function = "SALT12";
1651 groups = "SALT12";
1652 };
1653
1654 pinctrl_salt13_default: salt13_default {
1655 function = "SALT13";
1656 groups = "SALT13";
1657 };
1658
1659 pinctrl_salt14_default: salt14_default {
1660 function = "SALT14";
1661 groups = "SALT14";
1662 };
1663
1664 pinctrl_salt2_default: salt2_default {
1665 function = "SALT2";
1666 groups = "SALT2";
1667 };
1668
1669 pinctrl_salt3_default: salt3_default {
1670 function = "SALT3";
1671 groups = "SALT3";
1672 };
1673
1674 pinctrl_salt4_default: salt4_default {
1675 function = "SALT4";
1676 groups = "SALT4";
1677 };
1678
1679 pinctrl_salt5_default: salt5_default {
1680 function = "SALT5";
1681 groups = "SALT5";
1682 };
1683
1684 pinctrl_salt6_default: salt6_default {
1685 function = "SALT6";
1686 groups = "SALT6";
1687 };
1688
1689 pinctrl_salt7_default: salt7_default {
1690 function = "SALT7";
1691 groups = "SALT7";
1692 };
1693
1694 pinctrl_salt8_default: salt8_default {
1695 function = "SALT8";
1696 groups = "SALT8";
1697 };
1698
1699 pinctrl_salt9_default: salt9_default {
1700 function = "SALT9";
1701 groups = "SALT9";
1702 };
1703
1704 pinctrl_scl1_default: scl1_default {
1705 function = "SCL1";
1706 groups = "SCL1";
1707 };
1708
1709 pinctrl_scl2_default: scl2_default {
1710 function = "SCL2";
1711 groups = "SCL2";
1712 };
1713
1714 pinctrl_sd1_default: sd1_default {
1715 function = "SD1";
1716 groups = "SD1";
1717 };
1718
1719 pinctrl_sd2_default: sd2_default {
1720 function = "SD2";
1721 groups = "SD2";
1722 };
1723
1724 pinctrl_emmc_default: emmc_default {
1725 function = "EMMC";
1726 groups = "EMMC";
1727 };
1728
1729 pinctrl_emmcg8_default: emmcg8_default {
1730 function = "EMMCG8";
1731 groups = "EMMCG8";
1732 };
1733
1734 pinctrl_sda1_default: sda1_default {
1735 function = "SDA1";
1736 groups = "SDA1";
1737 };
1738
1739 pinctrl_sda2_default: sda2_default {
1740 function = "SDA2";
1741 groups = "SDA2";
1742 };
1743
1744 pinctrl_sgps1_default: sgps1_default {
1745 function = "SGPS1";
1746 groups = "SGPS1";
1747 };
1748
1749 pinctrl_sgps2_default: sgps2_default {
1750 function = "SGPS2";
1751 groups = "SGPS2";
1752 };
1753
1754 pinctrl_sioonctrl_default: sioonctrl_default {
1755 function = "SIOONCTRL";
1756 groups = "SIOONCTRL";
1757 };
1758
1759 pinctrl_siopbi_default: siopbi_default {
1760 function = "SIOPBI";
1761 groups = "SIOPBI";
1762 };
1763
1764 pinctrl_siopbo_default: siopbo_default {
1765 function = "SIOPBO";
1766 groups = "SIOPBO";
1767 };
1768
1769 pinctrl_siopwreq_default: siopwreq_default {
1770 function = "SIOPWREQ";
1771 groups = "SIOPWREQ";
1772 };
1773
1774 pinctrl_siopwrgd_default: siopwrgd_default {
1775 function = "SIOPWRGD";
1776 groups = "SIOPWRGD";
1777 };
1778
1779 pinctrl_sios3_default: sios3_default {
1780 function = "SIOS3";
1781 groups = "SIOS3";
1782 };
1783
1784 pinctrl_sios5_default: sios5_default {
1785 function = "SIOS5";
1786 groups = "SIOS5";
1787 };
1788
1789 pinctrl_siosci_default: siosci_default {
1790 function = "SIOSCI";
1791 groups = "SIOSCI";
1792 };
1793
1794 pinctrl_spi1_default: spi1_default {
1795 function = "SPI1";
1796 groups = "SPI1";
1797 };
1798
1799 pinctrl_spi1cs1_default: spi1cs1_default {
1800 function = "SPI1CS1";
1801 groups = "SPI1CS1";
1802 };
1803
1804 pinctrl_spi1debug_default: spi1debug_default {
1805 function = "SPI1DEBUG";
1806 groups = "SPI1DEBUG";
1807 };
1808
1809 pinctrl_spi1passthru_default: spi1passthru_default {
1810 function = "SPI1PASSTHRU";
1811 groups = "SPI1PASSTHRU";
1812 };
1813
1814 pinctrl_spi2ck_default: spi2ck_default {
1815 function = "SPI2CK";
1816 groups = "SPI2CK";
1817 };
1818
1819 pinctrl_spi2cs0_default: spi2cs0_default {
1820 function = "SPI2CS0";
1821 groups = "SPI2CS0";
1822 };
1823
1824 pinctrl_spi2cs1_default: spi2cs1_default {
1825 function = "SPI2CS1";
1826 groups = "SPI2CS1";
1827 };
1828
1829 pinctrl_spi2miso_default: spi2miso_default {
1830 function = "SPI2MISO";
1831 groups = "SPI2MISO";
1832 };
1833
1834 pinctrl_spi2mosi_default: spi2mosi_default {
1835 function = "SPI2MOSI";
1836 groups = "SPI2MOSI";
1837 };
1838
1839 pinctrl_timer3_default: timer3_default {
1840 function = "TIMER3";
1841 groups = "TIMER3";
1842 };
1843
1844 pinctrl_timer4_default: timer4_default {
1845 function = "TIMER4";
1846 groups = "TIMER4";
1847 };
1848
1849 pinctrl_timer5_default: timer5_default {
1850 function = "TIMER5";
1851 groups = "TIMER5";
1852 };
1853
1854 pinctrl_timer6_default: timer6_default {
1855 function = "TIMER6";
1856 groups = "TIMER6";
1857 };
1858
1859 pinctrl_timer7_default: timer7_default {
1860 function = "TIMER7";
1861 groups = "TIMER7";
1862 };
1863
1864 pinctrl_timer8_default: timer8_default {
1865 function = "TIMER8";
1866 groups = "TIMER8";
1867 };
1868
1869 pinctrl_txd1_default: txd1_default {
1870 function = "TXD1";
1871 groups = "TXD1";
1872 };
1873
1874 pinctrl_txd2_default: txd2_default {
1875 function = "TXD2";
1876 groups = "TXD2";
1877 };
1878
1879 pinctrl_txd3_default: txd3_default {
1880 function = "TXD3";
1881 groups = "TXD3";
1882 };
1883
1884 pinctrl_txd4_default: txd4_default {
1885 function = "TXD4";
1886 groups = "TXD4";
1887 };
1888
1889 pinctrl_uart6_default: uart6_default {
1890 function = "UART6";
1891 groups = "UART6";
1892 };
1893
1894 pinctrl_usbcki_default: usbcki_default {
1895 function = "USBCKI";
1896 groups = "USBCKI";
1897 };
1898
1899 pinctrl_usb2ah_default: usb2ah_default {
1900 function = "USB2AH";
1901 groups = "USB2AH";
1902 };
1903
1904 pinctrl_usb11bhid_default: usb11bhid_default {
1905 function = "USB11BHID";
1906 groups = "USB11BHID";
1907 };
1908
1909 pinctrl_usb2bh_default: usb2bh_default {
1910 function = "USB2BH";
1911 groups = "USB2BH";
1912 };
1913
1914 pinctrl_vgabiosrom_default: vgabiosrom_default {
1915 function = "VGABIOSROM";
1916 groups = "VGABIOSROM";
1917 };
1918
1919 pinctrl_vgahs_default: vgahs_default {
1920 function = "VGAHS";
1921 groups = "VGAHS";
1922 };
1923
1924 pinctrl_vgavs_default: vgavs_default {
1925 function = "VGAVS";
1926 groups = "VGAVS";
1927 };
1928
1929 pinctrl_vpi24_default: vpi24_default {
1930 function = "VPI24";
1931 groups = "VPI24";
1932 };
1933
1934 pinctrl_vpo_default: vpo_default {
1935 function = "VPO";
1936 groups = "VPO";
1937 };
1938
1939 pinctrl_wdtrst1_default: wdtrst1_default {
1940 function = "WDTRST1";
1941 groups = "WDTRST1";
1942 };
1943
1944 pinctrl_wdtrst2_default: wdtrst2_default {
1945 function = "WDTRST2";
1946 groups = "WDTRST2";
1947 };
1948
1949 pinctrl_pcie0rc_default: pcie0rc_default {
1950 function = "PCIE0RC";
1951 groups = "PCIE0RC";
1952 };
1953
1954 pinctrl_pcie1rc_default: pcie1rc_default {
1955 function = "PCIE1RC";
1956 groups = "PCIE1RC";
1957 };
1958};