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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +09002/*
3 * Configuation settings for the Renesas Technology RSK 7203
4 *
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
6 * Copyright (C) 2008 Renesas Solutions Corp.
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +09007 */
8
9#ifndef __RSK7203_H
10#define __RSK7203_H
11
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090012#define CONFIG_CPU_SH7203 1
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090013
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090014#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
15
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020016#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090017#undef CONFIG_SHOW_BOOT_PROGRESS
18
19/* MEMORY */
20#define RSK7203_SDRAM_BASE 0x0C000000
21#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
22#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
23
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090024/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090026
27/* SCIF */
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090028#define CONFIG_CONS_SCIF0 1
29
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020030#define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE
31#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090032
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033#define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE
34#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090035
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020036#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
37#define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1
38#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
39#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090041
42/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
44#undef CONFIG_SYS_FLASH_QUIET_TEST
45#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
46#define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1
47#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
48#define CONFIG_SYS_MAX_FLASH_SECT 64
49#define CONFIG_SYS_MAX_FLASH_BANKS 1
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090050
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020051#define CONFIG_ENV_SECT_SIZE (64 * 1024)
52#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
54#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
55#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090056
57/* Board Clock */
58#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090059#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090060#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
Nobuhiro Iwamatsubefb5cc2014-01-08 14:57:30 +090061#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090062
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090063#endif /* __RSK7203_H */