Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2015 Freescale Semiconductor |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __LS1043ARDB_H__ |
| 7 | #define __LS1043ARDB_H__ |
| 8 | |
| 9 | #include "ls1043a_common.h" |
| 10 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 11 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 12 | #define CONFIG_DDR_CLK_FREQ 100000000 |
| 13 | |
| 14 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 15 | |
| 16 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 17 | /* Physical Memory Map */ |
| 18 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 19 | |
| 20 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 21 | |
Hou Zhiqiang | a43c3ac | 2017-02-06 11:29:00 +0800 | [diff] [blame] | 22 | #ifndef CONFIG_SPL |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 23 | #define CONFIG_SYS_DDR_RAW_TIMING |
York Sun | 9a57729 | 2017-09-28 08:42:13 -0700 | [diff] [blame] | 24 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ |
| 25 | #define CONFIG_FSL_DDR_BIST |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 26 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 27 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
York Sun | 9a57729 | 2017-09-28 08:42:13 -0700 | [diff] [blame] | 28 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 29 | |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 30 | #ifdef CONFIG_RAMBOOT_PBL |
| 31 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg |
| 32 | #endif |
| 33 | |
| 34 | #ifdef CONFIG_NAND_BOOT |
| 35 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg |
| 36 | #endif |
| 37 | |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 38 | #ifdef CONFIG_SD_BOOT |
| 39 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg |
York Sun | f7eed6b | 2017-09-28 08:42:16 -0700 | [diff] [blame] | 40 | #define CONFIG_CMD_SPL |
| 41 | #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 |
| 42 | #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 |
| 43 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 |
| 44 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 45 | #endif |
| 46 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 47 | /* |
| 48 | * NOR Flash Definitions |
| 49 | */ |
| 50 | #define CONFIG_SYS_NOR_CSPR_EXT (0x0) |
| 51 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
| 52 | #define CONFIG_SYS_NOR_CSPR \ |
| 53 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
| 54 | CSPR_PORT_SIZE_16 | \ |
| 55 | CSPR_MSEL_NOR | \ |
| 56 | CSPR_V) |
| 57 | |
| 58 | /* NOR Flash Timing Params */ |
| 59 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| 60 | CSOR_NOR_TRHZ_80) |
| 61 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ |
| 62 | FTIM0_NOR_TEADC(0x1) | \ |
| 63 | FTIM0_NOR_TAVDS(0x0) | \ |
| 64 | FTIM0_NOR_TEAHC(0xc)) |
| 65 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ |
| 66 | FTIM1_NOR_TRAD_NOR(0xb) | \ |
| 67 | FTIM1_NOR_TSEQRAD_NOR(0x9)) |
| 68 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ |
| 69 | FTIM2_NOR_TCH(0x4) | \ |
| 70 | FTIM2_NOR_TWPH(0x8) | \ |
| 71 | FTIM2_NOR_TWP(0x10)) |
| 72 | #define CONFIG_SYS_NOR_FTIM3 0 |
| 73 | #define CONFIG_SYS_IFC_CCR 0x01000000 |
| 74 | |
| 75 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 76 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 77 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 78 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 79 | |
| 80 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 81 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } |
| 82 | |
| 83 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
| 84 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
| 85 | |
| 86 | /* |
| 87 | * NAND Flash Definitions |
| 88 | */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 89 | #ifndef SPL_NO_IFC |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 90 | #define CONFIG_NAND_FSL_IFC |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 91 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 92 | |
| 93 | #define CONFIG_SYS_NAND_BASE 0x7e800000 |
| 94 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 95 | |
| 96 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
| 97 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 98 | | CSPR_PORT_SIZE_8 \ |
| 99 | | CSPR_MSEL_NAND \ |
| 100 | | CSPR_V) |
| 101 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
| 102 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 103 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 104 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 105 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ |
| 106 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ |
| 107 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ |
| 108 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ |
| 109 | |
| 110 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 111 | |
| 112 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ |
| 113 | FTIM0_NAND_TWP(0x18) | \ |
| 114 | FTIM0_NAND_TWCHT(0x7) | \ |
| 115 | FTIM0_NAND_TWH(0xa)) |
| 116 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
| 117 | FTIM1_NAND_TWBE(0x39) | \ |
| 118 | FTIM1_NAND_TRR(0xe) | \ |
| 119 | FTIM1_NAND_TRP(0x18)) |
| 120 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ |
| 121 | FTIM2_NAND_TREH(0xa) | \ |
| 122 | FTIM2_NAND_TWHRE(0x1e)) |
| 123 | #define CONFIG_SYS_NAND_FTIM3 0x0 |
| 124 | |
| 125 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 126 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 127 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 128 | |
| 129 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 130 | |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 131 | #ifdef CONFIG_NAND_BOOT |
| 132 | #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ |
| 133 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO |
Ruchika Gupta | ba68875 | 2017-04-17 18:07:18 +0530 | [diff] [blame] | 134 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 135 | #endif |
| 136 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 137 | /* |
| 138 | * CPLD |
| 139 | */ |
| 140 | #define CONFIG_SYS_CPLD_BASE 0x7fb00000 |
| 141 | #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE |
| 142 | |
| 143 | #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) |
| 144 | #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ |
| 145 | CSPR_PORT_SIZE_8 | \ |
| 146 | CSPR_MSEL_GPCM | \ |
| 147 | CSPR_V) |
| 148 | #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) |
| 149 | #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| 150 | CSOR_NOR_NOR_MODE_AVD_NOR | \ |
| 151 | CSOR_NOR_TRHZ_80) |
| 152 | |
| 153 | /* CPLD Timing parameters for IFC GPCM */ |
| 154 | #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ |
| 155 | FTIM0_GPCM_TEADC(0xf) | \ |
| 156 | FTIM0_GPCM_TEAHC(0xf)) |
| 157 | #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
| 158 | FTIM1_GPCM_TRAD(0x3f)) |
| 159 | #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
| 160 | FTIM2_GPCM_TCH(0xf) | \ |
| 161 | FTIM2_GPCM_TWP(0xff)) |
| 162 | #define CONFIG_SYS_CPLD_FTIM3 0x0 |
| 163 | |
| 164 | /* IFC Timing Params */ |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 165 | #ifdef CONFIG_TFABOOT |
| 166 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT |
| 167 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 168 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 169 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 170 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 171 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 172 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 173 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 174 | |
| 175 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 176 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
| 177 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
| 178 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
| 179 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 180 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 181 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 182 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 183 | #else |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 184 | #ifdef CONFIG_NAND_BOOT |
| 185 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 186 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 187 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| 188 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| 189 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 190 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 191 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 192 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 193 | |
| 194 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT |
| 195 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR |
| 196 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
| 197 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 198 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 199 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 200 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 201 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 202 | #else |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 203 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT |
| 204 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 205 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 206 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 207 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 208 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 209 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 210 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 211 | |
| 212 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 213 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
| 214 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
| 215 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
| 216 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 217 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 218 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 219 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 220 | #endif |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 221 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 222 | |
| 223 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT |
| 224 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR |
| 225 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK |
| 226 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR |
| 227 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 |
| 228 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 |
| 229 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 |
| 230 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 |
| 231 | |
| 232 | /* EEPROM */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 233 | #ifndef SPL_NO_EEPROM |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 234 | #define CONFIG_ID_EEPROM |
| 235 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 236 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 237 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 |
| 238 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 239 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 240 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 241 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 242 | |
| 243 | /* |
| 244 | * Environment |
| 245 | */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 246 | #ifndef SPL_NO_ENV |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 247 | #define CONFIG_ENV_OVERWRITE |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 248 | #endif |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 249 | |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 250 | #ifdef CONFIG_TFABOOT |
| 251 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 252 | |
| 253 | #define CONFIG_ENV_SIZE 0x2000 |
| 254 | #define CONFIG_ENV_OFFSET 0x500000 |
| 255 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) |
| 256 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
| 257 | #else |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 258 | #if defined(CONFIG_NAND_BOOT) |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 259 | #define CONFIG_ENV_SIZE 0x2000 |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 260 | #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 261 | #elif defined(CONFIG_SD_BOOT) |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 262 | #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 263 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 264 | #define CONFIG_ENV_SIZE 0x2000 |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 265 | #else |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 266 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 267 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
| 268 | #define CONFIG_ENV_SIZE 0x20000 |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 269 | #endif |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 270 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 271 | |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 272 | /* FMan */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 273 | #ifndef SPL_NO_FMAN |
York Sun | 5f0580c | 2017-04-25 08:39:52 -0700 | [diff] [blame] | 274 | #define AQR105_IRQ_MASK 0x40000000 |
| 275 | |
| 276 | #ifdef CONFIG_NET |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 277 | #define CONFIG_PHY_VITESSE |
| 278 | #define CONFIG_PHY_REALTEK |
York Sun | 5f0580c | 2017-04-25 08:39:52 -0700 | [diff] [blame] | 279 | #endif |
| 280 | |
| 281 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 282 | #define CONFIG_FMAN_ENET |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 283 | |
| 284 | #define RGMII_PHY1_ADDR 0x1 |
| 285 | #define RGMII_PHY2_ADDR 0x2 |
| 286 | |
| 287 | #define QSGMII_PORT1_PHY_ADDR 0x4 |
| 288 | #define QSGMII_PORT2_PHY_ADDR 0x5 |
| 289 | #define QSGMII_PORT3_PHY_ADDR 0x6 |
| 290 | #define QSGMII_PORT4_PHY_ADDR 0x7 |
| 291 | |
| 292 | #define FM1_10GEC1_PHY_ADDR 0x1 |
| 293 | |
| 294 | #define CONFIG_ETHPRIME "FM1@DTSEC3" |
| 295 | #endif |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 296 | #endif |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 297 | |
Po Liu | 2271aa1 | 2016-05-18 10:09:38 +0800 | [diff] [blame] | 298 | /* SATA */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 299 | #ifndef SPL_NO_SATA |
Po Liu | 2271aa1 | 2016-05-18 10:09:38 +0800 | [diff] [blame] | 300 | #ifndef CONFIG_CMD_EXT2 |
| 301 | #define CONFIG_CMD_EXT2 |
| 302 | #endif |
Po Liu | 2271aa1 | 2016-05-18 10:09:38 +0800 | [diff] [blame] | 303 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 |
| 304 | #define CONFIG_SYS_SCSI_MAX_LUN 2 |
| 305 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
| 306 | CONFIG_SYS_SCSI_MAX_LUN) |
| 307 | #define SCSI_VEND_ID 0x1b4b |
| 308 | #define SCSI_DEV_ID 0x9170 |
| 309 | #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 310 | #endif |
Po Liu | 2271aa1 | 2016-05-18 10:09:38 +0800 | [diff] [blame] | 311 | |
Aneesh Bansal | b3e9820 | 2015-12-08 13:54:29 +0530 | [diff] [blame] | 312 | #include <asm/fsl_secure_boot.h> |
| 313 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 314 | #endif /* __LS1043ARDB_H__ */ |