Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 32ef937d806dfa48a03e47f4169ed14ad4e56539 / . / configs / rock_defconfig
blob: d7f11310cba18f9f61d69565e311ab162548a58d [file] [log] [blame]
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
3CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]4# CONFIG_SPL_USE_ARCH_MEMCPY is not set
5# CONFIG_SPL_USE_ARCH_MEMSET is not set
6CONFIG_ARCH_ROCKCHIP=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]7CONFIG_TEXT_BASE=0x60000000
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]8CONFIG_SYS_MALLOC_F_LEN=0x2000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]9CONFIG_NR_DRAM_BANKS=1
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]10CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
11CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]12CONFIG_SF_DEFAULT_SPEED=20000000
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]13CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]14CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]15CONFIG_ROCKCHIP_RK3188=y
Johan Jonkerf6fc8952022-04-09 18:55:02 +0200[diff] [blame]16# CONFIG_ROCKCHIP_STIMER is not set
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]17CONFIG_TARGET_ROCK=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]18CONFIG_SPL_STACK_R_ADDR=0x60080000
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]19CONFIG_SPL_STACK=0x10087fff
Tom Rini27280b62024-11-12 13:45:12 -0600[diff] [blame]20CONFIG_SPL_TEXT_BASE=0x10080800
Tom Rinib9dc6842024-04-22 17:24:09 -0600[diff] [blame]21CONFIG_SPL_STACK_R=y
22CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rinic427a582024-10-08 09:18:32 -0600[diff] [blame]23CONFIG_SYS_LOAD_ADDR=0x60800800
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]24CONFIG_DEBUG_UART_BASE=0x20064000
25CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]26CONFIG_DEBUG_UART=y
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]27CONFIG_USE_PREBOOT=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]28CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]29# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]30CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]31CONFIG_SPL_MAX_SIZE=0x7800
32CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]33CONFIG_SPL_NO_BSS_LIMIT=y
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]34# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]35CONFIG_CMD_I2C=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]36CONFIG_CMD_MMC=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]37CONFIG_CMD_SPI=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]38# CONFIG_CMD_SETEXPR is not set
39CONFIG_CMD_CACHE=y
40CONFIG_CMD_TIME=y
41CONFIG_CMD_REGULATOR=y
42CONFIG_SPL_OF_CONTROL=y
43CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
44CONFIG_SPL_OF_PLATDATA=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]45CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]46CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]47CONFIG_REGMAP=y
48CONFIG_SYSCON=y
49# CONFIG_SPL_SIMPLE_BUS is not set
50CONFIG_CLK=y
51CONFIG_ROCKCHIP_GPIO=y
52CONFIG_SYS_I2C_ROCKCHIP=y
53CONFIG_LED=y
54CONFIG_MMC_DW=y
55CONFIG_MMC_DW_ROCKCHIP=y
56CONFIG_PINCTRL=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]57CONFIG_DM_PMIC=y
58# CONFIG_SPL_PMIC_CHILDREN is not set
59CONFIG_PMIC_ACT8846=y
60CONFIG_REGULATOR_ACT8846=y
61CONFIG_DM_REGULATOR_FIXED=y
62CONFIG_RAM=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]63CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]64CONFIG_SYS_NS16550_MEM32=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]65CONFIG_ROCKCHIP_SERIAL=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]66CONFIG_SYSRESET=y
Tom Rini2cbc1202018-04-28 10:45:55 -0400[diff] [blame]67CONFIG_TIMER=y
68CONFIG_SPL_TIMER=y
69CONFIG_ROCKCHIP_TIMER=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]70CONFIG_USB=y
71CONFIG_ROCKCHIP_USB2_PHY=y
Tom Rini914a8c02024-01-03 09:26:16 -0500[diff] [blame]72CONFIG_RANDOM_UUID=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]73CONFIG_SPL_TINY_MEMSET=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]74CONFIG_CMD_DHRYSTONE=y
75CONFIG_ERRNO_STR=y