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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Lei Wen142c8f92011-06-28 21:50:06 +00002/*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
Lei Wen142c8f92011-06-28 21:50:06 +00006 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9
10#include <common.h>
Simon Glass63334482019-11-14 12:57:39 -070011#include <cpu_func.h>
Faiz Abbasf08f9d72019-06-11 00:43:34 +053012#include <dm.h>
Simon Glassb0842072016-06-12 23:30:27 -060013#include <errno.h>
Lei Wen142c8f92011-06-28 21:50:06 +000014#include <malloc.h>
15#include <mmc.h>
16#include <sdhci.h>
T Karthik Reddyc8a0ec02019-06-25 13:39:04 +020017#include <dm.h>
Lei Wen142c8f92011-06-28 21:50:06 +000018
Lei Wen142c8f92011-06-28 21:50:06 +000019static void sdhci_reset(struct sdhci_host *host, u8 mask)
20{
21 unsigned long timeout;
22
23 /* Wait max 100 ms */
24 timeout = 100;
25 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
26 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
27 if (timeout == 0) {
Darwin Rambo43558132013-12-19 15:13:25 -080028 printf("%s: Reset 0x%x never completed.\n",
29 __func__, (int)mask);
Lei Wen142c8f92011-06-28 21:50:06 +000030 return;
31 }
32 timeout--;
33 udelay(1000);
34 }
35}
36
37static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
38{
39 int i;
40 if (cmd->resp_type & MMC_RSP_136) {
41 /* CRC is stripped so we need to do some shifting. */
42 for (i = 0; i < 4; i++) {
43 cmd->response[i] = sdhci_readl(host,
44 SDHCI_RESPONSE + (3-i)*4) << 8;
45 if (i != 3)
46 cmd->response[i] |= sdhci_readb(host,
47 SDHCI_RESPONSE + (3-i)*4-1);
48 }
49 } else {
50 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
51 }
52}
53
54static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
55{
56 int i;
57 char *offs;
58 for (i = 0; i < data->blocksize; i += 4) {
59 offs = data->dest + i;
60 if (data->flags == MMC_DATA_READ)
61 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
62 else
63 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
64 }
65}
Faiz Abbas4c082a62019-04-16 23:06:58 +053066
67#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
68static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len,
69 bool end)
70{
71 struct sdhci_adma_desc *desc;
72 u8 attr;
73
74 desc = &host->adma_desc_table[host->desc_slot];
75
76 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
77 if (!end)
78 host->desc_slot++;
79 else
80 attr |= ADMA_DESC_ATTR_END;
81
82 desc->attr = attr;
83 desc->len = len;
84 desc->reserved = 0;
85 desc->addr_lo = (dma_addr_t)buf;
86#ifdef CONFIG_DMA_ADDR_T_64BIT
87 desc->addr_hi = (u64)buf >> 32;
88#endif
89}
90
91static void sdhci_prepare_adma_table(struct sdhci_host *host,
92 struct mmc_data *data)
93{
94 uint trans_bytes = data->blocksize * data->blocks;
95 uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
96 int i = desc_count;
97 char *buf;
98
99 host->desc_slot = 0;
100
101 if (data->flags & MMC_DATA_READ)
102 buf = data->dest;
103 else
104 buf = (char *)data->src;
105
106 while (--i) {
107 sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false);
108 buf += ADMA_MAX_LEN;
109 trans_bytes -= ADMA_MAX_LEN;
110 }
111
112 sdhci_adma_desc(host, buf, trans_bytes, true);
113
114 flush_cache((dma_addr_t)host->adma_desc_table,
115 ROUND(desc_count * sizeof(struct sdhci_adma_desc),
116 ARCH_DMA_MINALIGN));
117}
118#elif defined(CONFIG_MMC_SDHCI_SDMA)
119static void sdhci_prepare_adma_table(struct sdhci_host *host,
120 struct mmc_data *data)
121{}
122#endif
123#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
Faiz Abbas87102502019-04-16 23:06:57 +0530124static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
125 int *is_aligned, int trans_bytes)
126{
Jaehoon Chungf77f0582012-09-20 20:31:55 +0000127 unsigned char ctrl;
Faiz Abbas87102502019-04-16 23:06:57 +0530128
129 if (data->flags == MMC_DATA_READ)
130 host->start_addr = (dma_addr_t)data->dest;
131 else
132 host->start_addr = (dma_addr_t)data->src;
133
Juhyun \(Justin\) Oh7d48a732013-09-13 18:06:00 +0000134 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Jaehoon Chungf77f0582012-09-20 20:31:55 +0000135 ctrl &= ~SDHCI_CTRL_DMA_MASK;
Faiz Abbas4c082a62019-04-16 23:06:58 +0530136 if (host->flags & USE_ADMA64)
137 ctrl |= SDHCI_CTRL_ADMA64;
138 else if (host->flags & USE_ADMA)
139 ctrl |= SDHCI_CTRL_ADMA32;
Juhyun \(Justin\) Oh7d48a732013-09-13 18:06:00 +0000140 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Faiz Abbas87102502019-04-16 23:06:57 +0530141
Faiz Abbas4c082a62019-04-16 23:06:58 +0530142 if (host->flags & USE_SDMA) {
Masahiro Yamada32d12132020-02-14 16:40:22 +0900143 if (host->force_align_buffer ||
144 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
145 (host->start_addr & 0x7) != 0x0)) {
Faiz Abbas4c082a62019-04-16 23:06:58 +0530146 *is_aligned = 0;
Masahiro Yamadac3a17af2020-02-14 16:40:21 +0900147 host->start_addr = (unsigned long)host->align_buffer;
Faiz Abbas4c082a62019-04-16 23:06:58 +0530148 if (data->flags != MMC_DATA_READ)
Masahiro Yamadac3a17af2020-02-14 16:40:21 +0900149 memcpy(host->align_buffer, data->src,
150 trans_bytes);
Faiz Abbas4c082a62019-04-16 23:06:58 +0530151 }
Faiz Abbas4c082a62019-04-16 23:06:58 +0530152 sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
Faiz Abbas4c082a62019-04-16 23:06:58 +0530153 } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
154 sdhci_prepare_adma_table(host, data);
155
156 sdhci_writel(host, (u32)host->adma_addr, SDHCI_ADMA_ADDRESS);
157 if (host->flags & USE_ADMA64)
158 sdhci_writel(host, (u64)host->adma_addr >> 32,
159 SDHCI_ADMA_ADDRESS_HI);
160 }
161
Faiz Abbas87102502019-04-16 23:06:57 +0530162 flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN));
163}
164#else
165static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
166 int *is_aligned, int trans_bytes)
167{}
Jaehoon Chungf77f0582012-09-20 20:31:55 +0000168#endif
Faiz Abbas87102502019-04-16 23:06:57 +0530169static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
170{
171 dma_addr_t start_addr = host->start_addr;
172 unsigned int stat, rdy, mask, timeout, block = 0;
173 bool transfer_done = false;
Lei Wen142c8f92011-06-28 21:50:06 +0000174
Jaehoon Chung30686bd2012-09-20 20:31:54 +0000175 timeout = 1000000;
Lei Wen142c8f92011-06-28 21:50:06 +0000176 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
177 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
178 do {
179 stat = sdhci_readl(host, SDHCI_INT_STATUS);
180 if (stat & SDHCI_INT_ERROR) {
Masahiro Yamada45256c42017-12-30 02:00:12 +0900181 pr_debug("%s: Error detected in status(0x%X)!\n",
182 __func__, stat);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900183 return -EIO;
Lei Wen142c8f92011-06-28 21:50:06 +0000184 }
Alex Deymod9b70232017-04-02 01:24:34 -0700185 if (!transfer_done && (stat & rdy)) {
Lei Wen142c8f92011-06-28 21:50:06 +0000186 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
187 continue;
188 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
189 sdhci_transfer_pio(host, data);
190 data->dest += data->blocksize;
Alex Deymod9b70232017-04-02 01:24:34 -0700191 if (++block >= data->blocks) {
192 /* Keep looping until the SDHCI_INT_DATA_END is
193 * cleared, even if we finished sending all the
194 * blocks.
195 */
196 transfer_done = true;
197 continue;
198 }
Lei Wen142c8f92011-06-28 21:50:06 +0000199 }
Faiz Abbas4c082a62019-04-16 23:06:58 +0530200 if ((host->flags & USE_DMA) && !transfer_done &&
Faiz Abbas87102502019-04-16 23:06:57 +0530201 (stat & SDHCI_INT_DMA_END)) {
Lei Wen142c8f92011-06-28 21:50:06 +0000202 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
Faiz Abbas4c082a62019-04-16 23:06:58 +0530203 if (host->flags & USE_SDMA) {
204 start_addr &=
205 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
206 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
207 sdhci_writel(host, start_addr,
208 SDHCI_DMA_ADDRESS);
209 }
Lei Wen142c8f92011-06-28 21:50:06 +0000210 }
Lei Wen6c13c662011-10-08 04:14:57 +0000211 if (timeout-- > 0)
212 udelay(10);
213 else {
Darwin Rambo43558132013-12-19 15:13:25 -0800214 printf("%s: Transfer data timeout\n", __func__);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900215 return -ETIMEDOUT;
Lei Wen6c13c662011-10-08 04:14:57 +0000216 }
Lei Wen142c8f92011-06-28 21:50:06 +0000217 } while (!(stat & SDHCI_INT_DATA_END));
218 return 0;
219}
220
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200221/*
222 * No command will be sent by driver if card is busy, so driver must wait
223 * for card ready state.
224 * Every time when card is busy after timeout then (last) timeout value will be
225 * increased twice but only if it doesn't exceed global defined maximum.
Masahiro Yamada96250112016-08-25 16:07:39 +0900226 * Each function call will use last timeout value.
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200227 */
Masahiro Yamada96250112016-08-25 16:07:39 +0900228#define SDHCI_CMD_MAX_TIMEOUT 3200
Masahiro Yamadad4512312016-08-25 16:07:38 +0900229#define SDHCI_CMD_DEFAULT_TIMEOUT 100
Steve Raed4780832016-06-29 13:42:01 -0700230#define SDHCI_READ_STATUS_TIMEOUT 1000
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200231
Simon Glasseba48f92017-07-29 11:35:31 -0600232#ifdef CONFIG_DM_MMC
Simon Glassb97f0fa2016-06-12 23:30:28 -0600233static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
234 struct mmc_data *data)
235{
236 struct mmc *mmc = mmc_get_mmc_dev(dev);
237
238#else
Jeroen Hofsteeee54c7b2014-10-08 22:57:43 +0200239static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
Simon Glassb97f0fa2016-06-12 23:30:28 -0600240 struct mmc_data *data)
Lei Wen142c8f92011-06-28 21:50:06 +0000241{
Simon Glassb97f0fa2016-06-12 23:30:28 -0600242#endif
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200243 struct sdhci_host *host = mmc->priv;
Lei Wen142c8f92011-06-28 21:50:06 +0000244 unsigned int stat = 0;
245 int ret = 0;
246 int trans_bytes = 0, is_aligned = 1;
247 u32 mask, flags, mode;
Faiz Abbas87102502019-04-16 23:06:57 +0530248 unsigned int time = 0;
Simon Glass97c78e82016-05-14 14:03:04 -0600249 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
Vipul Kumardbad7b42018-05-03 12:20:54 +0530250 ulong start = get_timer(0);
Lei Wen142c8f92011-06-28 21:50:06 +0000251
Faiz Abbas87102502019-04-16 23:06:57 +0530252 host->start_addr = 0;
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200253 /* Timeout unit - ms */
Masahiro Yamadad4512312016-08-25 16:07:38 +0900254 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
Lei Wen142c8f92011-06-28 21:50:06 +0000255
Lei Wen142c8f92011-06-28 21:50:06 +0000256 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
257
258 /* We shouldn't wait for data inihibit for stop commands, even
259 though they might use busy signaling */
Siva Durga Prasad Paladugudb620bd2018-04-19 12:37:05 +0530260 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
Siva Durga Prasad Paladugub97e99f2018-06-13 11:43:01 +0530261 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
262 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
Lei Wen142c8f92011-06-28 21:50:06 +0000263 mask &= ~SDHCI_DATA_INHIBIT;
264
265 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200266 if (time >= cmd_timeout) {
Darwin Rambo43558132013-12-19 15:13:25 -0800267 printf("%s: MMC: %d busy ", __func__, mmc_dev);
Masahiro Yamada96250112016-08-25 16:07:39 +0900268 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200269 cmd_timeout += cmd_timeout;
270 printf("timeout increasing to: %u ms.\n",
271 cmd_timeout);
272 } else {
273 puts("timeout.\n");
Jaehoon Chung7825d202016-07-19 16:33:36 +0900274 return -ECOMM;
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200275 }
Lei Wen142c8f92011-06-28 21:50:06 +0000276 }
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200277 time++;
Lei Wen142c8f92011-06-28 21:50:06 +0000278 udelay(1000);
279 }
280
Jorge Ramirez-Ortiz65da8be2017-11-02 15:10:21 +0100281 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
282
Lei Wen142c8f92011-06-28 21:50:06 +0000283 mask = SDHCI_INT_RESPONSE;
Siva Durga Prasad Paladugub97e99f2018-06-13 11:43:01 +0530284 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
285 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
Siva Durga Prasad Paladugudb620bd2018-04-19 12:37:05 +0530286 mask = SDHCI_INT_DATA_AVAIL;
287
Lei Wen142c8f92011-06-28 21:50:06 +0000288 if (!(cmd->resp_type & MMC_RSP_PRESENT))
289 flags = SDHCI_CMD_RESP_NONE;
290 else if (cmd->resp_type & MMC_RSP_136)
291 flags = SDHCI_CMD_RESP_LONG;
292 else if (cmd->resp_type & MMC_RSP_BUSY) {
293 flags = SDHCI_CMD_RESP_SHORT_BUSY;
Jaehoon Chungd0d1b252016-07-12 21:18:46 +0900294 if (data)
295 mask |= SDHCI_INT_DATA_END;
Lei Wen142c8f92011-06-28 21:50:06 +0000296 } else
297 flags = SDHCI_CMD_RESP_SHORT;
298
299 if (cmd->resp_type & MMC_RSP_CRC)
300 flags |= SDHCI_CMD_CRC;
301 if (cmd->resp_type & MMC_RSP_OPCODE)
302 flags |= SDHCI_CMD_INDEX;
Siva Durga Prasad Paladugu5d88ba72018-05-29 20:03:10 +0530303 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
304 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
Lei Wen142c8f92011-06-28 21:50:06 +0000305 flags |= SDHCI_CMD_DATA;
306
Darwin Rambo43558132013-12-19 15:13:25 -0800307 /* Set Transfer mode regarding to data flag */
Heinrich Schuchardt730636b2017-11-10 21:13:34 +0100308 if (data) {
Lei Wen142c8f92011-06-28 21:50:06 +0000309 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
310 mode = SDHCI_TRNS_BLK_CNT_EN;
311 trans_bytes = data->blocks * data->blocksize;
312 if (data->blocks > 1)
313 mode |= SDHCI_TRNS_MULTI;
314
315 if (data->flags == MMC_DATA_READ)
316 mode |= SDHCI_TRNS_READ;
317
Faiz Abbas4c082a62019-04-16 23:06:58 +0530318 if (host->flags & USE_DMA) {
Faiz Abbas87102502019-04-16 23:06:57 +0530319 mode |= SDHCI_TRNS_DMA;
320 sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
Lei Wen142c8f92011-06-28 21:50:06 +0000321 }
322
Lei Wen142c8f92011-06-28 21:50:06 +0000323 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
324 data->blocksize),
325 SDHCI_BLOCK_SIZE);
326 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
327 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
Kevin Liu8e5db912015-03-23 17:57:00 -0500328 } else if (cmd->resp_type & MMC_RSP_BUSY) {
329 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
Lei Wen142c8f92011-06-28 21:50:06 +0000330 }
331
332 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
Lei Wen142c8f92011-06-28 21:50:06 +0000333 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
Stefan Roese42817a42015-06-29 14:58:08 +0200334 start = get_timer(0);
Lei Wen142c8f92011-06-28 21:50:06 +0000335 do {
336 stat = sdhci_readl(host, SDHCI_INT_STATUS);
337 if (stat & SDHCI_INT_ERROR)
338 break;
Lei Wen142c8f92011-06-28 21:50:06 +0000339
Masahiro Yamadaa63aaa02016-07-10 00:40:22 +0900340 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
341 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
342 return 0;
343 } else {
344 printf("%s: Timeout for status update!\n",
345 __func__);
Jaehoon Chung7825d202016-07-19 16:33:36 +0900346 return -ETIMEDOUT;
Masahiro Yamadaa63aaa02016-07-10 00:40:22 +0900347 }
Jaehoon Chung89237a82012-04-23 02:36:25 +0000348 }
Masahiro Yamadaa63aaa02016-07-10 00:40:22 +0900349 } while ((stat & mask) != mask);
Jaehoon Chung89237a82012-04-23 02:36:25 +0000350
Lei Wen142c8f92011-06-28 21:50:06 +0000351 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
352 sdhci_cmd_done(host, cmd);
353 sdhci_writel(host, mask, SDHCI_INT_STATUS);
354 } else
355 ret = -1;
356
357 if (!ret && data)
Faiz Abbas87102502019-04-16 23:06:57 +0530358 ret = sdhci_transfer_data(host, data);
Lei Wen142c8f92011-06-28 21:50:06 +0000359
Tushar Behera0fba4c22012-09-20 20:31:57 +0000360 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
361 udelay(1000);
362
Lei Wen142c8f92011-06-28 21:50:06 +0000363 stat = sdhci_readl(host, SDHCI_INT_STATUS);
364 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
365 if (!ret) {
366 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
367 !is_aligned && (data->flags == MMC_DATA_READ))
Masahiro Yamadac3a17af2020-02-14 16:40:21 +0900368 memcpy(data->dest, host->align_buffer, trans_bytes);
Lei Wen142c8f92011-06-28 21:50:06 +0000369 return 0;
370 }
371
372 sdhci_reset(host, SDHCI_RESET_CMD);
373 sdhci_reset(host, SDHCI_RESET_DATA);
374 if (stat & SDHCI_INT_TIMEOUT)
Jaehoon Chung7825d202016-07-19 16:33:36 +0900375 return -ETIMEDOUT;
Lei Wen142c8f92011-06-28 21:50:06 +0000376 else
Jaehoon Chung7825d202016-07-19 16:33:36 +0900377 return -ECOMM;
Lei Wen142c8f92011-06-28 21:50:06 +0000378}
379
Siva Durga Prasad Paladugu1f67b492018-04-19 12:37:07 +0530380#if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
381static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
382{
383 int err;
384 struct mmc *mmc = mmc_get_mmc_dev(dev);
385 struct sdhci_host *host = mmc->priv;
386
387 debug("%s\n", __func__);
388
Ramon Friedcf6ba6f2018-05-14 15:02:30 +0300389 if (host->ops && host->ops->platform_execute_tuning) {
Siva Durga Prasad Paladugu1f67b492018-04-19 12:37:07 +0530390 err = host->ops->platform_execute_tuning(mmc, opcode);
391 if (err)
392 return err;
393 return 0;
394 }
395 return 0;
396}
397#endif
Faiz Abbasab619662019-06-11 00:43:35 +0530398int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
Lei Wen142c8f92011-06-28 21:50:06 +0000399{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200400 struct sdhci_host *host = mmc->priv;
Stefan Roesee9161032016-12-12 08:34:42 +0100401 unsigned int div, clk = 0, timeout;
Wenyou Yang09456d92015-09-22 14:59:25 +0800402
403 /* Wait max 20 ms */
404 timeout = 200;
405 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
406 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
407 if (timeout == 0) {
408 printf("%s: Timeout to wait cmd & data inhibit\n",
409 __func__);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900410 return -EBUSY;
Wenyou Yang09456d92015-09-22 14:59:25 +0800411 }
412
413 timeout--;
414 udelay(100);
415 }
Lei Wen142c8f92011-06-28 21:50:06 +0000416
Stefan Roesee9161032016-12-12 08:34:42 +0100417 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
Lei Wen142c8f92011-06-28 21:50:06 +0000418
419 if (clock == 0)
420 return 0;
421
Ramon Friedcf6ba6f2018-05-14 15:02:30 +0300422 if (host->ops && host->ops->set_delay)
Siva Durga Prasad Paladugu1f67b492018-04-19 12:37:07 +0530423 host->ops->set_delay(host);
424
Jaehoon Chung46e627c2013-07-19 17:44:49 +0900425 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Wenyou Yang3d734042016-09-18 09:01:22 +0800426 /*
427 * Check if the Host Controller supports Programmable Clock
428 * Mode.
429 */
430 if (host->clk_mul) {
431 for (div = 1; div <= 1024; div++) {
Wenyou Yangab877fe2017-04-26 09:32:30 +0800432 if ((host->max_clk / div) <= clock)
Lei Wen142c8f92011-06-28 21:50:06 +0000433 break;
434 }
Wenyou Yang3d734042016-09-18 09:01:22 +0800435
436 /*
437 * Set Programmable Clock Mode in the Clock
438 * Control register.
439 */
440 clk = SDHCI_PROG_CLOCK_MODE;
441 div--;
442 } else {
443 /* Version 3.00 divisors must be a multiple of 2. */
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100444 if (host->max_clk <= clock) {
Wenyou Yang3d734042016-09-18 09:01:22 +0800445 div = 1;
446 } else {
447 for (div = 2;
448 div < SDHCI_MAX_DIV_SPEC_300;
449 div += 2) {
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100450 if ((host->max_clk / div) <= clock)
Wenyou Yang3d734042016-09-18 09:01:22 +0800451 break;
452 }
453 }
454 div >>= 1;
Lei Wen142c8f92011-06-28 21:50:06 +0000455 }
456 } else {
457 /* Version 2.00 divisors must be a power of 2. */
458 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100459 if ((host->max_clk / div) <= clock)
Lei Wen142c8f92011-06-28 21:50:06 +0000460 break;
461 }
Wenyou Yang3d734042016-09-18 09:01:22 +0800462 div >>= 1;
Lei Wen142c8f92011-06-28 21:50:06 +0000463 }
Lei Wen142c8f92011-06-28 21:50:06 +0000464
Masahiro Yamadaeeb91ad2017-01-13 11:51:51 +0900465 if (host->ops && host->ops->set_clock)
Jaehoon Chung46d3c032016-12-30 15:30:18 +0900466 host->ops->set_clock(host, div);
Jaehoon Chungb1929ea2012-08-30 16:24:11 +0000467
Wenyou Yang3d734042016-09-18 09:01:22 +0800468 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
Lei Wen142c8f92011-06-28 21:50:06 +0000469 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
470 << SDHCI_DIVIDER_HI_SHIFT;
471 clk |= SDHCI_CLOCK_INT_EN;
472 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
473
474 /* Wait max 20 ms */
475 timeout = 20;
476 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
477 & SDHCI_CLOCK_INT_STABLE)) {
478 if (timeout == 0) {
Darwin Rambo43558132013-12-19 15:13:25 -0800479 printf("%s: Internal clock never stabilised.\n",
480 __func__);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900481 return -EBUSY;
Lei Wen142c8f92011-06-28 21:50:06 +0000482 }
483 timeout--;
484 udelay(1000);
485 }
486
487 clk |= SDHCI_CLOCK_CARD_EN;
488 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
489 return 0;
490}
491
492static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
493{
494 u8 pwr = 0;
495
496 if (power != (unsigned short)-1) {
497 switch (1 << power) {
498 case MMC_VDD_165_195:
499 pwr = SDHCI_POWER_180;
500 break;
501 case MMC_VDD_29_30:
502 case MMC_VDD_30_31:
503 pwr = SDHCI_POWER_300;
504 break;
505 case MMC_VDD_32_33:
506 case MMC_VDD_33_34:
507 pwr = SDHCI_POWER_330;
508 break;
509 }
510 }
511
512 if (pwr == 0) {
513 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
514 return;
515 }
516
517 pwr |= SDHCI_POWER_ON;
518
519 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
520}
521
Faiz Abbas2eddc002019-06-11 00:43:40 +0530522void sdhci_set_uhs_timing(struct sdhci_host *host)
523{
524 struct mmc *mmc = (struct mmc *)host->mmc;
525 u32 reg;
526
527 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
528 reg &= ~SDHCI_CTRL_UHS_MASK;
529
530 switch (mmc->selected_mode) {
531 case UHS_SDR50:
532 case MMC_HS_52:
533 reg |= SDHCI_CTRL_UHS_SDR50;
534 break;
535 case UHS_DDR50:
536 case MMC_DDR_52:
537 reg |= SDHCI_CTRL_UHS_DDR50;
538 break;
539 case UHS_SDR104:
540 case MMC_HS_200:
541 reg |= SDHCI_CTRL_UHS_SDR104;
542 break;
543 default:
544 reg |= SDHCI_CTRL_UHS_SDR12;
545 }
546
547 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
548}
549
Simon Glasseba48f92017-07-29 11:35:31 -0600550#ifdef CONFIG_DM_MMC
Simon Glassb97f0fa2016-06-12 23:30:28 -0600551static int sdhci_set_ios(struct udevice *dev)
552{
553 struct mmc *mmc = mmc_get_mmc_dev(dev);
554#else
Jaehoon Chungb6cd1d32016-12-30 15:30:16 +0900555static int sdhci_set_ios(struct mmc *mmc)
Lei Wen142c8f92011-06-28 21:50:06 +0000556{
Simon Glassb97f0fa2016-06-12 23:30:28 -0600557#endif
Lei Wen142c8f92011-06-28 21:50:06 +0000558 u32 ctrl;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200559 struct sdhci_host *host = mmc->priv;
Lei Wen142c8f92011-06-28 21:50:06 +0000560
Masahiro Yamadaeeb91ad2017-01-13 11:51:51 +0900561 if (host->ops && host->ops->set_control_reg)
Jaehoon Chung46d3c032016-12-30 15:30:18 +0900562 host->ops->set_control_reg(host);
Jaehoon Chung53889ed2012-04-23 02:36:26 +0000563
Lei Wen142c8f92011-06-28 21:50:06 +0000564 if (mmc->clock != host->clock)
565 sdhci_set_clock(mmc, mmc->clock);
566
Siva Durga Prasad Paladugu9fccd8a2018-04-19 12:37:04 +0530567 if (mmc->clk_disable)
568 sdhci_set_clock(mmc, 0);
569
Lei Wen142c8f92011-06-28 21:50:06 +0000570 /* Set bus width */
571 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
572 if (mmc->bus_width == 8) {
573 ctrl &= ~SDHCI_CTRL_4BITBUS;
Jaehoon Chung46e627c2013-07-19 17:44:49 +0900574 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
575 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wen142c8f92011-06-28 21:50:06 +0000576 ctrl |= SDHCI_CTRL_8BITBUS;
577 } else {
Matt Reimer9651f592015-02-19 11:22:53 -0700578 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
579 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wen142c8f92011-06-28 21:50:06 +0000580 ctrl &= ~SDHCI_CTRL_8BITBUS;
581 if (mmc->bus_width == 4)
582 ctrl |= SDHCI_CTRL_4BITBUS;
583 else
584 ctrl &= ~SDHCI_CTRL_4BITBUS;
585 }
586
587 if (mmc->clock > 26000000)
588 ctrl |= SDHCI_CTRL_HISPD;
589 else
590 ctrl &= ~SDHCI_CTRL_HISPD;
591
Hannes Schmelzer576a0182018-03-07 08:00:56 +0100592 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
593 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
Jaehoon Chung53889ed2012-04-23 02:36:26 +0000594 ctrl &= ~SDHCI_CTRL_HISPD;
595
Lei Wen142c8f92011-06-28 21:50:06 +0000596 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Jaehoon Chungb6cd1d32016-12-30 15:30:16 +0900597
Stefan Roesea3554ef2016-12-12 08:24:56 +0100598 /* If available, call the driver specific "post" set_ios() function */
599 if (host->ops && host->ops->set_ios_post)
Faiz Abbas375acf82019-06-11 00:43:37 +0530600 return host->ops->set_ios_post(host);
Stefan Roesea3554ef2016-12-12 08:24:56 +0100601
Simon Glassb97f0fa2016-06-12 23:30:28 -0600602 return 0;
Lei Wen142c8f92011-06-28 21:50:06 +0000603}
604
Jeroen Hofsteeee54c7b2014-10-08 22:57:43 +0200605static int sdhci_init(struct mmc *mmc)
Lei Wen142c8f92011-06-28 21:50:06 +0000606{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200607 struct sdhci_host *host = mmc->priv;
T Karthik Reddy3863f7e2019-06-25 13:39:03 +0200608#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
609 struct udevice *dev = mmc->dev;
610
Baruch Siach6b907192019-07-22 19:14:06 +0300611 gpio_request_by_name(dev, "cd-gpios", 0,
T Karthik Reddy3863f7e2019-06-25 13:39:03 +0200612 &host->cd_gpio, GPIOD_IS_IN);
613#endif
Lei Wen142c8f92011-06-28 21:50:06 +0000614
Masahiro Yamadaea04d902016-08-25 16:07:34 +0900615 sdhci_reset(host, SDHCI_RESET_ALL);
616
Masahiro Yamadac3a17af2020-02-14 16:40:21 +0900617#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
618 host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
Masahiro Yamada32d12132020-02-14 16:40:22 +0900619 /*
620 * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
621 * is defined.
622 */
623 host->force_align_buffer = true;
Masahiro Yamadac3a17af2020-02-14 16:40:21 +0900624#else
625 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
626 host->align_buffer = memalign(8, 512 * 1024);
627 if (!host->align_buffer) {
Darwin Rambo43558132013-12-19 15:13:25 -0800628 printf("%s: Aligned buffer alloc failed!!!\n",
629 __func__);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900630 return -ENOMEM;
Lei Wen142c8f92011-06-28 21:50:06 +0000631 }
632 }
Masahiro Yamadac3a17af2020-02-14 16:40:21 +0900633#endif
Lei Wen142c8f92011-06-28 21:50:06 +0000634
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200635 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
Joe Hershberger456f34a2012-08-17 10:18:55 +0000636
Masahiro Yamadaeeb91ad2017-01-13 11:51:51 +0900637 if (host->ops && host->ops->get_cd)
Jaehoon Chung730a5952016-12-30 15:30:15 +0900638 host->ops->get_cd(host);
Joe Hershberger456f34a2012-08-17 10:18:55 +0000639
Łukasz Majewskid56a52a2013-01-11 05:08:54 +0000640 /* Enable only interrupts served by the SD controller */
Darwin Rambo43558132013-12-19 15:13:25 -0800641 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
642 SDHCI_INT_ENABLE);
Łukasz Majewskid56a52a2013-01-11 05:08:54 +0000643 /* Mask all sdhci interrupt sources */
644 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
Lei Wen142c8f92011-06-28 21:50:06 +0000645
Lei Wen142c8f92011-06-28 21:50:06 +0000646 return 0;
647}
648
Simon Glasseba48f92017-07-29 11:35:31 -0600649#ifdef CONFIG_DM_MMC
Simon Glassb97f0fa2016-06-12 23:30:28 -0600650int sdhci_probe(struct udevice *dev)
651{
652 struct mmc *mmc = mmc_get_mmc_dev(dev);
653
654 return sdhci_init(mmc);
655}
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200656
Baruch Siach4c280a92019-11-03 12:00:27 +0200657static int sdhci_get_cd(struct udevice *dev)
T Karthik Reddyc8a0ec02019-06-25 13:39:04 +0200658{
659 struct mmc *mmc = mmc_get_mmc_dev(dev);
660 struct sdhci_host *host = mmc->priv;
661 int value;
662
663 /* If nonremovable, assume that the card is always present. */
664 if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
665 return 1;
666 /* If polling, assume that the card is always present. */
667 if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
668 return 1;
669
670#if CONFIG_IS_ENABLED(DM_GPIO)
671 value = dm_gpio_get_value(&host->cd_gpio);
672 if (value >= 0) {
673 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
674 return !value;
675 else
676 return value;
677 }
678#endif
679 value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
680 SDHCI_CARD_PRESENT);
681 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
682 return !value;
683 else
684 return value;
685}
686
Simon Glassb97f0fa2016-06-12 23:30:28 -0600687const struct dm_mmc_ops sdhci_ops = {
688 .send_cmd = sdhci_send_command,
689 .set_ios = sdhci_set_ios,
T Karthik Reddyc8a0ec02019-06-25 13:39:04 +0200690 .get_cd = sdhci_get_cd,
Siva Durga Prasad Paladugu1f67b492018-04-19 12:37:07 +0530691#ifdef MMC_SUPPORTS_TUNING
692 .execute_tuning = sdhci_execute_tuning,
693#endif
Simon Glassb97f0fa2016-06-12 23:30:28 -0600694};
695#else
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200696static const struct mmc_ops sdhci_ops = {
697 .send_cmd = sdhci_send_command,
698 .set_ios = sdhci_set_ios,
699 .init = sdhci_init,
700};
Simon Glassb97f0fa2016-06-12 23:30:28 -0600701#endif
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200702
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900703int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100704 u32 f_max, u32 f_min)
Lei Wen142c8f92011-06-28 21:50:06 +0000705{
Siva Durga Prasad Paladuguc0290b42018-04-19 12:37:08 +0530706 u32 caps, caps_1 = 0;
Faiz Abbasf08f9d72019-06-11 00:43:34 +0530707#if CONFIG_IS_ENABLED(DM_MMC)
T Karthik Reddy2a1b6632019-09-02 16:34:31 +0200708 u64 dt_caps, dt_caps_mask;
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900709
T Karthik Reddy2a1b6632019-09-02 16:34:31 +0200710 dt_caps_mask = dev_read_u64_default(host->mmc->dev,
711 "sdhci-caps-mask", 0);
712 dt_caps = dev_read_u64_default(host->mmc->dev,
713 "sdhci-caps", 0);
714 caps = ~(u32)dt_caps_mask &
715 sdhci_readl(host, SDHCI_CAPABILITIES);
716 caps |= (u32)dt_caps;
Faiz Abbasf08f9d72019-06-11 00:43:34 +0530717#else
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900718 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
Faiz Abbasf08f9d72019-06-11 00:43:34 +0530719#endif
T Karthik Reddy2a1b6632019-09-02 16:34:31 +0200720 debug("%s, caps: 0x%x\n", __func__, caps);
Masahiro Yamada27bfb712016-08-25 16:07:37 +0900721
Masahiro Yamada124f6ce2016-12-07 22:10:29 +0900722#ifdef CONFIG_MMC_SDHCI_SDMA
Masahiro Yamada27bfb712016-08-25 16:07:37 +0900723 if (!(caps & SDHCI_CAN_DO_SDMA)) {
724 printf("%s: Your controller doesn't support SDMA!!\n",
725 __func__);
726 return -EINVAL;
727 }
Faiz Abbas87102502019-04-16 23:06:57 +0530728
729 host->flags |= USE_SDMA;
Masahiro Yamada27bfb712016-08-25 16:07:37 +0900730#endif
Faiz Abbas4c082a62019-04-16 23:06:58 +0530731#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
732 if (!(caps & SDHCI_CAN_DO_ADMA2)) {
733 printf("%s: Your controller doesn't support SDMA!!\n",
734 __func__);
735 return -EINVAL;
736 }
737 host->adma_desc_table = (struct sdhci_adma_desc *)
738 memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
739
740 host->adma_addr = (dma_addr_t)host->adma_desc_table;
741#ifdef CONFIG_DMA_ADDR_T_64BIT
742 host->flags |= USE_ADMA64;
743#else
744 host->flags |= USE_ADMA;
745#endif
746#endif
Jaehoon Chung6c5b3592016-09-26 08:10:01 +0900747 if (host->quirks & SDHCI_QUIRK_REG32_RW)
748 host->version =
749 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
750 else
751 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900752
753 cfg->name = host->name;
Simon Glasseba48f92017-07-29 11:35:31 -0600754#ifndef CONFIG_DM_MMC
Simon Glassb0842072016-06-12 23:30:27 -0600755 cfg->ops = &sdhci_ops;
Lei Wen142c8f92011-06-28 21:50:06 +0000756#endif
Wenyou Yangab877fe2017-04-26 09:32:30 +0800757
758 /* Check whether the clock multiplier is supported or not */
759 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Faiz Abbasf08f9d72019-06-11 00:43:34 +0530760#if CONFIG_IS_ENABLED(DM_MMC)
T Karthik Reddy2a1b6632019-09-02 16:34:31 +0200761 caps_1 = ~(u32)(dt_caps_mask >> 32) &
762 sdhci_readl(host, SDHCI_CAPABILITIES_1);
763 caps_1 |= (u32)(dt_caps >> 32);
Faiz Abbasf08f9d72019-06-11 00:43:34 +0530764#else
Wenyou Yangab877fe2017-04-26 09:32:30 +0800765 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
Faiz Abbasf08f9d72019-06-11 00:43:34 +0530766#endif
T Karthik Reddy2a1b6632019-09-02 16:34:31 +0200767 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
Wenyou Yangab877fe2017-04-26 09:32:30 +0800768 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
769 SDHCI_CLOCK_MUL_SHIFT;
770 }
771
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100772 if (host->max_clk == 0) {
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900773 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100774 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
Simon Glassb0842072016-06-12 23:30:27 -0600775 SDHCI_CLOCK_BASE_SHIFT;
Lei Wen142c8f92011-06-28 21:50:06 +0000776 else
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100777 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
Simon Glassb0842072016-06-12 23:30:27 -0600778 SDHCI_CLOCK_BASE_SHIFT;
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100779 host->max_clk *= 1000000;
Wenyou Yangab877fe2017-04-26 09:32:30 +0800780 if (host->clk_mul)
781 host->max_clk *= host->clk_mul;
Lei Wen142c8f92011-06-28 21:50:06 +0000782 }
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100783 if (host->max_clk == 0) {
Masahiro Yamadada957dd2016-08-25 16:07:35 +0900784 printf("%s: Hardware doesn't specify base clock frequency\n",
785 __func__);
Simon Glassb0842072016-06-12 23:30:27 -0600786 return -EINVAL;
Masahiro Yamadada957dd2016-08-25 16:07:35 +0900787 }
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100788 if (f_max && (f_max < host->max_clk))
789 cfg->f_max = f_max;
790 else
791 cfg->f_max = host->max_clk;
792 if (f_min)
793 cfg->f_min = f_min;
Lei Wen142c8f92011-06-28 21:50:06 +0000794 else {
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900795 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Simon Glassb0842072016-06-12 23:30:27 -0600796 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
Lei Wen142c8f92011-06-28 21:50:06 +0000797 else
Simon Glassb0842072016-06-12 23:30:27 -0600798 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
Lei Wen142c8f92011-06-28 21:50:06 +0000799 }
Simon Glassb0842072016-06-12 23:30:27 -0600800 cfg->voltages = 0;
Lei Wen142c8f92011-06-28 21:50:06 +0000801 if (caps & SDHCI_CAN_VDD_330)
Simon Glassb0842072016-06-12 23:30:27 -0600802 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
Lei Wen142c8f92011-06-28 21:50:06 +0000803 if (caps & SDHCI_CAN_VDD_300)
Simon Glassb0842072016-06-12 23:30:27 -0600804 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
Lei Wen142c8f92011-06-28 21:50:06 +0000805 if (caps & SDHCI_CAN_VDD_180)
Simon Glassb0842072016-06-12 23:30:27 -0600806 cfg->voltages |= MMC_VDD_165_195;
Jaehoon Chung53889ed2012-04-23 02:36:26 +0000807
Masahiro Yamada4b338772016-08-25 16:07:36 +0900808 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
809 cfg->voltages |= host->voltages;
810
Masahiro Yamadaea5b7c02017-12-30 02:00:08 +0900811 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
Jaehoon Chungbc00a542016-12-30 15:30:21 +0900812
813 /* Since Host Controller Version3.0 */
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900814 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Jaehoon Chung665152e2016-12-30 15:30:11 +0900815 if (!(caps & SDHCI_CAN_DO_8BIT))
816 cfg->host_caps &= ~MMC_MODE_8BIT;
Jagannadha Sutradharudu Teki08706be2013-05-21 15:01:36 +0530817 }
Siva Durga Prasad Paladugub0fbb492016-01-12 15:12:15 +0530818
Hannes Schmelzer576a0182018-03-07 08:00:56 +0100819 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
820 cfg->host_caps &= ~MMC_MODE_HS;
821 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
822 }
823
Siva Durga Prasad Paladuguc0290b42018-04-19 12:37:08 +0530824 if (!(cfg->voltages & MMC_VDD_165_195) ||
825 (host->quirks & SDHCI_QUIRK_NO_1_8_V))
826 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
827 SDHCI_SUPPORT_DDR50);
828
829 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
830 SDHCI_SUPPORT_DDR50))
831 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
832
833 if (caps_1 & SDHCI_SUPPORT_SDR104) {
834 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
835 /*
836 * SD3.0: SDR104 is supported so (for eMMC) the caps2
837 * field can be promoted to support HS200.
838 */
839 cfg->host_caps |= MMC_CAP(MMC_HS_200);
840 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
841 cfg->host_caps |= MMC_CAP(UHS_SDR50);
842 }
843
844 if (caps_1 & SDHCI_SUPPORT_DDR50)
845 cfg->host_caps |= MMC_CAP(UHS_DDR50);
846
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900847 if (host->host_caps)
848 cfg->host_caps |= host->host_caps;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200849
Simon Glassb0842072016-06-12 23:30:27 -0600850 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
851
852 return 0;
853}
854
Simon Glassb97f0fa2016-06-12 23:30:28 -0600855#ifdef CONFIG_BLK
856int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
857{
858 return mmc_bind(dev, mmc, cfg);
859}
860#else
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100861int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
Simon Glassb0842072016-06-12 23:30:27 -0600862{
Masahiro Yamadada957dd2016-08-25 16:07:35 +0900863 int ret;
864
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100865 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
Masahiro Yamadada957dd2016-08-25 16:07:35 +0900866 if (ret)
867 return ret;
Simon Glassb0842072016-06-12 23:30:27 -0600868
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200869 host->mmc = mmc_create(&host->cfg, host);
870 if (host->mmc == NULL) {
871 printf("%s: mmc create fail!\n", __func__);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900872 return -ENOMEM;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200873 }
Lei Wen142c8f92011-06-28 21:50:06 +0000874
875 return 0;
876}
Simon Glassb97f0fa2016-06-12 23:30:28 -0600877#endif