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git01.mediatek.com / filogic / uboot / 32a8db0ca0d4d2d927895fa9e096032081813def / . / arch / arm / dts / tegra30-colibri.dts
blob: 487e1f6ae54cc6abde7b8a30f7c17a5b55408815 [file] [log] [blame]
Stefan Agner60bae8c2014-08-05 23:27:30 +0200[diff] [blame]1/dts-v1/;
2
3#include "tegra30.dtsi"
4
5/ {
6 model = "Toradex Colibri T30";
7 compatible = "toradex,colibri_t30", "nvidia,tegra30";
8
Marcel Ziswilera60d8dd2014-10-11 00:10:40 +0200[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Stefan Agner60bae8c2014-08-05 23:27:30 +0200[diff] [blame]13 aliases {
14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c700";
17 sdhci0 = "/sdhci@78000600";
18 sdhci1 = "/sdhci@78000200";
Simon Glassb4381ee2014-10-13 23:42:12 -0600[diff] [blame]19 spi0 = "/spi@7000d400";
Stefan Agner60bae8c2014-08-05 23:27:30 +0200[diff] [blame]20 usb0 = "/usb@7d000000";
21 usb1 = "/usb@7d004000"; /* on module only, for ASIX */
22 usb2 = "/usb@7d008000";
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0x80000000 0x40000000>;
28 };
29
Marcel Ziswilerb89e6ac2014-10-02 18:23:11 +0200[diff] [blame]30 /*
31 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
32 * board)
33 */
Stefan Agner60bae8c2014-08-05 23:27:30 +0200[diff] [blame]34 i2c@7000c000 {
35 status = "okay";
36 clock-frequency = <100000>;
37 };
38
39 /* GEN2_I2C: unused */
40
41 /* CAM_I2C: unused */
42
43 /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
44 i2c@7000c700 {
45 status = "okay";
46 clock-frequency = <100000>;
47 };
48
Marcel Ziswilerb89e6ac2014-10-02 18:23:11 +0200[diff] [blame]49 /*
50 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
51 * touch screen controller
52 */
Stefan Agner60bae8c2014-08-05 23:27:30 +0200[diff] [blame]53 i2c@7000d000 {
54 status = "okay";
55 clock-frequency = <100000>;
56 };
57
58 /* SPI1: Colibri SSP */
59 spi@7000d400 {
60 status = "okay";
61 spi-max-frequency = <25000000>;
62 };
63
64 sdhci@78000200 {
65 status = "okay";
66 bus-width = <4>;
Marcel Ziswiler7c358d02015-03-01 02:05:37 +0100[diff] [blame]67 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
Stefan Agner60bae8c2014-08-05 23:27:30 +0200[diff] [blame]68 };
69
70 sdhci@78000600 {
71 status = "okay";
72 bus-width = <8>;
73 non-removable;
74 };
75
76 /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
77 usb@7d000000 {
78 status = "okay";
Marcel Ziswileradcb8522015-08-06 00:47:12 +0200[diff] [blame]79 dr_mode = "otg";
Stefan Agner60bae8c2014-08-05 23:27:30 +0200[diff] [blame]80 };
81
82 /* EHCI instance 1: USB2_DP/N -> AX88772B */
83 usb@7d004000 {
84 status = "okay";
Marcel Ziswiler7c358d02015-03-01 02:05:37 +0100[diff] [blame]85 /* VBUS_LAN */
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]86 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
Marcel Ziswiler764d4122015-08-06 00:47:10 +0200[diff] [blame]87 phy_type = "utmi";
Stefan Agner60bae8c2014-08-05 23:27:30 +0200[diff] [blame]88 };
89
90 /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
91 usb@7d008000 {
92 status = "okay";
Marcel Ziswiler7c358d02015-03-01 02:05:37 +0100[diff] [blame]93 /* USBH_PEN */
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]94 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
Stefan Agner60bae8c2014-08-05 23:27:30 +0200[diff] [blame]95 };
96};