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Angus Ainslie3f8667c2022-08-25 06:46:02 -07001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2017 NXP
4 * Copyright 2018 Emcraft Systems
5 * Copyright 2022 Purism
6 *
7 */
8
9#ifndef __LIBREM5_H
10#define __LIBREM5_H
11
12/* #define DEBUG */
13
14#include <version.h>
15#include <linux/sizes.h>
16#include <asm/arch/imx-regs.h>
17
Tom Rini376b88a2022-10-28 20:27:13 -040018#define CFG_SYS_FSL_USDHC_NUM 2
Angus Ainslie3f8667c2022-08-25 06:46:02 -070019
Angus Ainslie3f8667c2022-08-25 06:46:02 -070020#define CONSOLE_ON_UART1
21
22#ifdef CONSOLE_ON_UART1
Tom Rinia17aa192022-12-04 10:04:55 -050023#define CFG_MXC_UART_BASE UART1_BASE_ADDR
Angus Ainslie3f8667c2022-08-25 06:46:02 -070024#define CONSOLE_UART_CLK 0
25#define CONSOLE "ttymxc0"
26#elif defined(CONSOLE_ON_UART2)
Tom Rinia17aa192022-12-04 10:04:55 -050027#define CFG_MXC_UART_BASE UART2_BASE_ADDR
Angus Ainslie3f8667c2022-08-25 06:46:02 -070028#define CONSOLE_UART_CLK 1
29#define CONSOLE "ttymxc1"
30#elif defined(CONSOLE_ON_UART3)
Tom Rinia17aa192022-12-04 10:04:55 -050031#define CFG_MXC_UART_BASE UART3_BASE_ADDR
Angus Ainslie3f8667c2022-08-25 06:46:02 -070032#define CONSOLE_UART_CLK 2
33#define CONSOLE "ttymxc2"
34#elif defined(CONSOLE_ON_UART4)
Tom Rinia17aa192022-12-04 10:04:55 -050035#define CFG_MXC_UART_BASE UART4_BASE_ADDR
Angus Ainslie3f8667c2022-08-25 06:46:02 -070036#define CONSOLE_UART_CLK 3
37#define CONSOLE "ttymxc3"
38#else
Tom Rinia17aa192022-12-04 10:04:55 -050039#define CFG_MXC_UART_BASE UART1_BASE_ADDR
Angus Ainslie3f8667c2022-08-25 06:46:02 -070040#define CONSOLE_UART_CLK 0
41#define CONSOLE "ttymxc0"
42#endif
43
Simon Glass209ae762024-09-29 19:49:49 -060044#ifndef CONFIG_XPL_BUILD
Angus Ainslie3f8667c2022-08-25 06:46:02 -070045#define BOOT_TARGET_DEVICES(func) \
46 func(MMC, mmc, 0) \
47 func(USB, usb, 0) \
48 func(DHCP, dhcp, na)
49#include <config_distro_bootcmd.h>
50#else
51#define BOOTENV
52#endif
53
54/* Initial environment variables */
Tom Rinic9edebe2022-12-04 10:03:50 -050055#define CFG_EXTRA_ENV_SETTINGS \
Angus Ainslie3f8667c2022-08-25 06:46:02 -070056 "scriptaddr=0x80000000\0" \
57 "pxefile_addr_r=0x80100000\0" \
58 "kernel_addr_r=0x80800000\0" \
Arnaud Ferraris0a9fd0b2023-10-27 15:40:45 +020059 "kernel_comp_addr_r=0x90000000\0" \
60 "kernel_comp_size=0x08000000\0" \
Angus Ainslie3f8667c2022-08-25 06:46:02 -070061 "fdt_addr_r=0x84800000\0" \
62 "ramdisk_addr_r=0x85000000\0" \
63 "console=" CONSOLE ",115200\0" \
64 "bootargs=u_boot_version=" PLAIN_VERSION "\0" \
65 "stdin=usbacm,serial\0" \
66 "stdout=usbacm,serial\0" \
67 "stderr=usbacm,serial\0" \
68 BOOTENV
69
70/* Link Definitions */
71
Tom Rini6a5dccc2022-11-16 13:10:41 -050072#define CFG_SYS_INIT_RAM_ADDR 0x40000000
73#define CFG_SYS_INIT_RAM_SIZE 0x80000
Angus Ainslie3f8667c2022-08-25 06:46:02 -070074
Tom Rinibb4dd962022-11-16 13:10:37 -050075#define CFG_SYS_SDRAM_BASE 0x40000000
Angus Ainslie3f8667c2022-08-25 06:46:02 -070076#define PHYS_SDRAM 0x40000000
77#define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */
78
79/* Monitor Command Prompt */
80
Tom Rini376b88a2022-10-28 20:27:13 -040081#define CFG_SYS_FSL_ESDHC_ADDR 0
Angus Ainslie3f8667c2022-08-25 06:46:02 -070082
83#endif