| Patrice Chotard | cad450c | 2022-04-27 13:54:00 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_STM32=y |
| 3 | CONFIG_SYS_TEXT_BASE=0x08008000 |
| 4 | CONFIG_SYS_MALLOC_LEN=0x100000 |
| 5 | CONFIG_SYS_MALLOC_F_LEN=0xE00 |
| 6 | CONFIG_SPL_GPIO=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_NR_DRAM_BANKS=1 |
| 10 | CONFIG_ENV_SIZE=0x2000 |
| 11 | CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval" |
| 12 | CONFIG_SPL_TEXT_BASE=0x8000000 |
| Tom Rini | ce53ec8 | 2022-08-23 15:24:14 -0400 | [diff] [blame] | 13 | CONFIG_SYS_PROMPT="U-Boot > " |
| Patrice Chotard | cad450c | 2022-04-27 13:54:00 +0200 | [diff] [blame] | 14 | CONFIG_SPL_SERIAL=y |
| 15 | CONFIG_SPL_DRIVERS_MISC=y |
| 16 | CONFIG_STM32F7=y |
| 17 | CONFIG_TARGET_STM32F746_DISCO=y |
| 18 | CONFIG_SPL=y |
| Tom Rini | 2e34053 | 2022-05-23 13:56:21 -0400 | [diff] [blame] | 19 | CONFIG_SYS_LOAD_ADDR=0x8008000 |
| Patrice Chotard | cad450c | 2022-04-27 13:54:00 +0200 | [diff] [blame] | 20 | CONFIG_BUILD_TARGET="u-boot-with-spl.bin" |
| 21 | CONFIG_DISTRO_DEFAULTS=y |
| Tom Rini | 4ddbade | 2022-05-25 12:16:03 -0400 | [diff] [blame] | 22 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 23 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 |
| Patrice Chotard | cad450c | 2022-04-27 13:54:00 +0200 | [diff] [blame] | 24 | CONFIG_BOOTDELAY=3 |
| 25 | CONFIG_AUTOBOOT_KEYED=y |
| 26 | CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" |
| 27 | CONFIG_AUTOBOOT_STOP_STR=" " |
| 28 | CONFIG_USE_BOOTARGS=y |
| 29 | CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" |
| 30 | # CONFIG_DISPLAY_CPUINFO is not set |
| 31 | CONFIG_BOARD_LATE_INIT=y |
| Tom Rini | abb0f52 | 2022-05-16 17:20:26 -0400 | [diff] [blame] | 32 | CONFIG_SPL_PAD_TO=0x8000 |
| Tom Rini | 0cb89e7 | 2022-05-19 15:09:22 -0400 | [diff] [blame] | 33 | CONFIG_SPL_NO_BSS_LIMIT=y |
| Patrice Chotard | cad450c | 2022-04-27 13:54:00 +0200 | [diff] [blame] | 34 | CONFIG_SPL_BOARD_INIT=y |
| 35 | CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
| 36 | CONFIG_SPL_MTD_SUPPORT=y |
| 37 | CONFIG_SPL_XIP_SUPPORT=y |
| Tom Rini | 2c9d2b5 | 2022-05-27 22:06:52 -0400 | [diff] [blame] | 38 | CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000 |
| Patrice Chotard | cad450c | 2022-04-27 13:54:00 +0200 | [diff] [blame] | 39 | CONFIG_SPL_DM_RESET=y |
| Tom Rini | cbfa139 | 2022-05-11 17:38:09 -0400 | [diff] [blame] | 40 | CONFIG_SYS_PBSIZE=1050 |
| Patrice Chotard | cad450c | 2022-04-27 13:54:00 +0200 | [diff] [blame] | 41 | CONFIG_CMD_GPT=y |
| 42 | # CONFIG_RANDOM_UUID is not set |
| 43 | CONFIG_CMD_MMC=y |
| 44 | # CONFIG_CMD_SETEXPR is not set |
| 45 | CONFIG_CMD_SNTP=y |
| 46 | CONFIG_CMD_DNS=y |
| 47 | CONFIG_CMD_LINK_LOCAL=y |
| 48 | CONFIG_CMD_BMP=y |
| 49 | CONFIG_CMD_CACHE=y |
| 50 | CONFIG_CMD_TIMER=y |
| 51 | # CONFIG_ISO_PARTITION is not set |
| 52 | CONFIG_OF_CONTROL=y |
| 53 | CONFIG_SPL_OF_CONTROL=y |
| 54 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 55 | CONFIG_NET_RANDOM_ETHADDR=y |
| 56 | CONFIG_NETCONSOLE=y |
| 57 | CONFIG_SPL_DM=y |
| 58 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 59 | CONFIG_SPL_OF_TRANSLATE=y |
| 60 | CONFIG_SPL_CLK=y |
| 61 | CONFIG_ARM_PL180_MMCI=y |
| 62 | CONFIG_MTD=y |
| 63 | CONFIG_DM_MTD=y |
| 64 | CONFIG_MTD_NOR_FLASH=y |
| 65 | CONFIG_STM32_FLASH=y |
| Tom Rini | d38112c | 2022-07-23 13:05:04 -0400 | [diff] [blame] | 66 | CONFIG_SYS_MAX_FLASH_SECT=8 |
| Patrice Chotard | cad450c | 2022-04-27 13:54:00 +0200 | [diff] [blame] | 67 | CONFIG_DM_SPI_FLASH=y |
| 68 | CONFIG_SPI_FLASH_MACRONIX=y |
| 69 | CONFIG_SPI_FLASH_STMICRO=y |
| 70 | CONFIG_PHY_SMSC=y |
| Patrice Chotard | cad450c | 2022-04-27 13:54:00 +0200 | [diff] [blame] | 71 | CONFIG_ETH_DESIGNWARE=y |
| Tom Rini | 7ac21a3 | 2022-06-15 12:03:43 -0400 | [diff] [blame] | 72 | CONFIG_DW_ALTDESCRIPTOR=y |
| Patrice Chotard | cad450c | 2022-04-27 13:54:00 +0200 | [diff] [blame] | 73 | CONFIG_MII=y |
| 74 | # CONFIG_PINCTRL_FULL is not set |
| 75 | CONFIG_SPL_PINCTRL=y |
| 76 | CONFIG_SPL_RAM=y |
| 77 | CONFIG_SPECIFY_CONSOLE_INDEX=y |
| 78 | CONFIG_SPI=y |
| 79 | CONFIG_DM_SPI=y |
| 80 | CONFIG_STM32_QSPI=y |
| 81 | CONFIG_SPL_TIMER=y |
| 82 | CONFIG_DM_VIDEO=y |
| 83 | CONFIG_BACKLIGHT_GPIO=y |
| 84 | CONFIG_VIDEO_STM32=y |
| 85 | CONFIG_VIDEO_STM32_MAX_XRES=480 |
| 86 | CONFIG_VIDEO_STM32_MAX_YRES=640 |
| 87 | CONFIG_SPLASH_SCREEN=y |
| 88 | CONFIG_SPLASH_SCREEN_ALIGN=y |
| 89 | CONFIG_VIDEO_BMP_RLE8=y |
| 90 | CONFIG_BMP_16BPP=y |
| 91 | CONFIG_BMP_24BPP=y |
| 92 | CONFIG_BMP_32BPP=y |
| 93 | CONFIG_OF_LIBFDT_OVERLAY=y |