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Dirk Behmea1aa39c2008-12-14 09:47:12 +01001/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Dirk Behmea1aa39c2008-12-14 09:47:12 +01008 */
9
10#ifndef _OMAP3_H_
11#define _OMAP3_H_
12
13/* Stuff on L3 Interconnect */
14#define SMX_APE_BASE 0x68000000
15
16/* GPMC */
17#define OMAP34XX_GPMC_BASE 0x6E000000
18
19/* SMS */
20#define OMAP34XX_SMS_BASE 0x6C000000
21
22/* SDRC */
23#define OMAP34XX_SDRC_BASE 0x6D000000
24
25/*
26 * L4 Peripherals - L4 Wakeup and L4 Core now
27 */
28#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
29#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
Dirk Behme12dbcf62009-03-12 19:30:50 +010030#define OMAP34XX_ID_L4_IO_BASE 0x4830A200
Dirk Behmea1aa39c2008-12-14 09:47:12 +010031#define OMAP34XX_L4_PER 0x49000000
32#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
33
Simon Schwarza56688c2011-09-28 05:00:24 +000034/* DMA4/SDMA */
35#define OMAP34XX_DMA4_BASE 0x48056000
36
Dirk Behmea1aa39c2008-12-14 09:47:12 +010037/* CONTROL */
38#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
39
Steve Kipiszbf7438a2011-04-18 17:27:00 -040040#ifndef __ASSEMBLY__
41/* Signal Integrity Parameter Control Registers */
42struct control_prog_io {
43 unsigned char res[0x408];
44 unsigned int io2; /* 0x408 */
45 unsigned char res2[0x38];
46 unsigned int io0; /* 0x444 */
47 unsigned int io1; /* 0x448 */
48};
49#endif /* __ASSEMBLY__ */
50
51/* Bit definition for CONTROL_PROG_IO1 */
52#define PRG_I2C2_PULLUPRESX 0x00000001
53
Dirk Behmea1aa39c2008-12-14 09:47:12 +010054/* UART */
55#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
56#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
57#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
Michael Trimarchi552846a2013-11-18 15:06:21 +010058#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000)
Dirk Behmea1aa39c2008-12-14 09:47:12 +010059
60/* General Purpose Timers */
61#define OMAP34XX_GPT1 0x48318000
62#define OMAP34XX_GPT2 0x49032000
63#define OMAP34XX_GPT3 0x49034000
64#define OMAP34XX_GPT4 0x49036000
65#define OMAP34XX_GPT5 0x49038000
66#define OMAP34XX_GPT6 0x4903A000
67#define OMAP34XX_GPT7 0x4903C000
68#define OMAP34XX_GPT8 0x4903E000
69#define OMAP34XX_GPT9 0x49040000
70#define OMAP34XX_GPT10 0x48086000
71#define OMAP34XX_GPT11 0x48088000
72#define OMAP34XX_GPT12 0x48304000
73
74/* WatchDog Timers (1 secure, 3 GP) */
75#define WD1_BASE 0x4830C000
76#define WD2_BASE 0x48314000
77#define WD3_BASE 0x49030000
78
79/* 32KTIMER */
80#define SYNC_32KTIMER_BASE 0x48320000
81
82#ifndef __ASSEMBLY__
83
Dirk Behmedc7af202009-08-08 09:30:21 +020084struct s32ktimer {
Dirk Behmea1aa39c2008-12-14 09:47:12 +010085 unsigned char res[0x10];
86 unsigned int s32k_cr; /* 0x10 */
Dirk Behmedc7af202009-08-08 09:30:21 +020087};
Dirk Behmea1aa39c2008-12-14 09:47:12 +010088
89#endif /* __ASSEMBLY__ */
90
Dirk Behmea1aa39c2008-12-14 09:47:12 +010091#ifndef __ASSEMBLY__
Dirk Behmedc7af202009-08-08 09:30:21 +020092struct gpio {
Dirk Behmea1aa39c2008-12-14 09:47:12 +010093 unsigned char res1[0x34];
94 unsigned int oe; /* 0x34 */
Dirk Behme78716112009-02-12 18:55:41 +010095 unsigned int datain; /* 0x38 */
96 unsigned char res2[0x54];
Dirk Behmea1aa39c2008-12-14 09:47:12 +010097 unsigned int cleardataout; /* 0x90 */
98 unsigned int setdataout; /* 0x94 */
Dirk Behmedc7af202009-08-08 09:30:21 +020099};
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100100#endif /* __ASSEMBLY__ */
101
102#define GPIO0 (0x1 << 0)
103#define GPIO1 (0x1 << 1)
104#define GPIO2 (0x1 << 2)
105#define GPIO3 (0x1 << 3)
106#define GPIO4 (0x1 << 4)
107#define GPIO5 (0x1 << 5)
108#define GPIO6 (0x1 << 6)
109#define GPIO7 (0x1 << 7)
110#define GPIO8 (0x1 << 8)
111#define GPIO9 (0x1 << 9)
112#define GPIO10 (0x1 << 10)
113#define GPIO11 (0x1 << 11)
114#define GPIO12 (0x1 << 12)
115#define GPIO13 (0x1 << 13)
116#define GPIO14 (0x1 << 14)
117#define GPIO15 (0x1 << 15)
118#define GPIO16 (0x1 << 16)
119#define GPIO17 (0x1 << 17)
120#define GPIO18 (0x1 << 18)
121#define GPIO19 (0x1 << 19)
122#define GPIO20 (0x1 << 20)
123#define GPIO21 (0x1 << 21)
124#define GPIO22 (0x1 << 22)
125#define GPIO23 (0x1 << 23)
126#define GPIO24 (0x1 << 24)
127#define GPIO25 (0x1 << 25)
128#define GPIO26 (0x1 << 26)
129#define GPIO27 (0x1 << 27)
130#define GPIO28 (0x1 << 28)
131#define GPIO29 (0x1 << 29)
132#define GPIO30 (0x1 << 30)
133#define GPIO31 (0x1 << 31)
134
135/* base address for indirect vectors (internal boot mode) */
136#define SRAM_OFFSET0 0x40000000
137#define SRAM_OFFSET1 0x00200000
138#define SRAM_OFFSET2 0x0000F800
139#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
140 SRAM_OFFSET2)
Aneesh V49a2e552011-11-21 23:34:01 +0000141#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64)
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100142
Enric Balletbò i Serra950abd02013-12-06 21:30:22 +0100143#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */
144#define NON_SECURE_SRAM_END 0x40210000
Aneesh Vd16dd012011-06-16 23:30:53 +0000145
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100146#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
147
Aneesh Vd16dd012011-06-16 23:30:53 +0000148/* scratch area - accessible on both EMU and GP */
Enric Balletbò i Serra950abd02013-12-06 21:30:22 +0100149#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START
Aneesh Vd16dd012011-06-16 23:30:53 +0000150
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100151#define DEBUG_LED1 149 /* gpio */
152#define DEBUG_LED2 150 /* gpio */
153
154#define XDR_POP 5 /* package on package part */
155#define SDR_DISCRETE 4 /* 128M memory SDR module */
156#define DDR_STACKED 3 /* stacked part on 2422 */
157#define DDR_COMBO 2 /* combo part on cpu daughter card */
158#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
159
160#define DDR_100 100 /* type found on most mem d-boards */
161#define DDR_111 111 /* some combo parts */
162#define DDR_133 133 /* most combo, some mem d-boards */
163#define DDR_165 165 /* future parts */
164
165#define CPU_3430 0x3430
166
167/*
168 * 343x real hardware:
169 * ES1 = rev 0
170 *
Sanjeev Premifcbb44f2009-04-27 21:27:54 +0530171 * ES2 onwards, the value maps to contents of IDCODE register [31:28].
Tom Rix096b9c22009-09-10 15:27:57 -0400172 *
173 * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing.
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100174 */
Sanjeev Premifcbb44f2009-04-27 21:27:54 +0530175#define CPU_3XX_ES10 0
176#define CPU_3XX_ES20 1
177#define CPU_3XX_ES21 2
178#define CPU_3XX_ES30 3
179#define CPU_3XX_ES31 4
Steve Sakomanad74ace2010-08-17 14:39:34 -0700180#define CPU_3XX_ES312 7
181#define CPU_3XX_MAX_REV 8
Sanjeev Premifcbb44f2009-04-27 21:27:54 +0530182
Howard D. Gray3082bc62011-09-04 14:11:17 -0400183/*
184 * 37xx real hardware:
185 * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
186 */
187
188#define CPU_37XX_ES10 0
189#define CPU_37XX_ES11 1
190#define CPU_37XX_ES12 2
191#define CPU_37XX_MAX_REV 3
192
Sanjeev Premifcbb44f2009-04-27 21:27:54 +0530193#define CPU_3XX_ID_SHIFT 28
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100194
195#define WIDTH_8BIT 0x0000
196#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
197
Steve Sakomanad74ace2010-08-17 14:39:34 -0700198/*
199 * Hawkeye values
200 */
201#define HAWKEYE_OMAP34XX 0xb7ae
202#define HAWKEYE_AM35XX 0xb868
203#define HAWKEYE_OMAP36XX 0xb891
204
205#define HAWKEYE_SHIFT 12
206
207/*
208 * Define CPU families
209 */
210#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
211#define CPU_AM35XX 0x3500 /* AM35xx devices */
212#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
213
214/*
215 * Control status register values corresponding to cpu variants
216 */
217#define OMAP3503 0x5c00
218#define OMAP3515 0x1c00
219#define OMAP3525 0x4c00
220#define OMAP3530 0x0c00
221
222#define AM3505 0x5c00
223#define AM3517 0x1c00
224
225#define OMAP3730 0x0c00
226
Aneesh Vd16dd012011-06-16 23:30:53 +0000227/*
228 * ROM code API related flags
229 */
230#define OMAP3_GP_ROMCODE_API_L2_INVAL 1
231#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3
232
233/*
234 * EMU device PPA HAL related flags
235 */
236#define OMAP3_EMU_HAL_API_L2_INVAL 40
237#define OMAP3_EMU_HAL_API_WRITE_ACR 42
238
239#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4
240
Andrii Tseglytskyi28095da2013-05-20 22:42:08 +0000241/* ABB settings */
242#define OMAP_ABB_SETTLING_TIME 30
243#define OMAP_ABB_CLOCK_CYCLES 8
244
245/* ABB tranxdone mask */
246#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26)
247
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100248#endif