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Michal Simek090a2d72018-03-27 10:36:39 +02001// SPDX-License-Identifier: GPL-2.0+
Michal Simekc9ce08d2017-11-02 11:42:12 +01002/*
3 * dts file for Xilinx ZynqMP ZCU102 Rev1.0
4 *
Michal Simek3f283ea2023-09-22 12:35:41 +02005 * (C) Copyright 2016 - 2018, Xilinx, Inc.
Michal Simekc9ce08d2017-11-02 11:42:12 +01006 *
Michal Simeka8c94362023-07-10 14:35:49 +02007 * Michal Simek <michal.simek@amd.com>
Michal Simekc9ce08d2017-11-02 11:42:12 +01008 */
9
10#include "zynqmp-zcu102-revB.dts"
11
12/ {
13 model = "ZynqMP ZCU102 Rev1.0";
14 compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
15};
16
Michal Simek0a2c32a2018-03-27 16:21:42 +020017&eeprom {
Michal Simekc9ce08d2017-11-02 11:42:12 +010018 #address-cells = <1>;
19 #size-cells = <1>;
20
Michal Simekc9f40782018-03-27 12:50:04 +020021 board_sn: board-sn@0 {
Michal Simekc9ce08d2017-11-02 11:42:12 +010022 reg = <0x0 0x14>;
23 };
24
Michal Simekc9f40782018-03-27 12:50:04 +020025 eth_mac: eth-mac@20 {
Michal Simekc9ce08d2017-11-02 11:42:12 +010026 reg = <0x20 0x6>;
27 };
28
Michal Simekc9f40782018-03-27 12:50:04 +020029 board_name: board-name@d0 {
Michal Simekc9ce08d2017-11-02 11:42:12 +010030 reg = <0xd0 0x6>;
31 };
32
Michal Simekc9f40782018-03-27 12:50:04 +020033 board_revision: board-revision@e0 {
Michal Simekc9ce08d2017-11-02 11:42:12 +010034 reg = <0xe0 0x3>;
35 };
36};