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git01.mediatek.com / filogic / uboot / 3181a8710675fd1e3cfb8b8279b2f21d551753da / . / arch / arm / dts / k3-j721s2-som-p0.dtsi
blob: a4006f3280273b14d5df20822aef11b28e039249 [file] [log] [blame]
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]3 * SoM: https://www.ti.com/lit/zip/sprr439
4 *
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8/dts-v1/;
9
10#include "k3-j721s2.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14 memory@80000000 {
15 device_type = "memory";
16 /* 16 GB RAM */
17 reg = <0x00 0x80000000 0x00 0x80000000>,
18 <0x08 0x80000000 0x03 0x80000000>;
19 };
20
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]21 /* Reserving memory regions still pending */
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]22 reserved_memory: reserved-memory {
23 #address-cells = <2>;
24 #size-cells = <2>;
25 ranges;
26
27 secure_ddr: optee@9e800000 {
28 reg = <0x00 0x9e800000 0x00 0x01800000>;
29 alignment = <0x1000>;
30 no-map;
31 };
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]32 };
33
34 mux0: mux-controller {
35 compatible = "gpio-mux";
36 #mux-state-cells = <1>;
37 mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
38 };
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]39
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]40 mux1: mux-controller {
41 compatible = "gpio-mux";
42 #mux-state-cells = <1>;
43 mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]44 };
45
46 transceiver0: can-phy0 {
47 /* standby pin has been grounded by default */
48 compatible = "ti,tcan1042";
49 #phy-cells = <0>;
50 max-bitrate = <5000000>;
51 };
52};
53
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]54&wkup_pmx0 {
55 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
56 pinctrl-single,pins = <
57 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
58 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
59 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
60 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
61 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
62 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
63 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
64 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
65 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
66 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
67 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
68 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
69 >;
70 };
71};
72
73&wkup_pmx2 {
74 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
75 pinctrl-single,pins = <
76 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
77 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
78 >;
79 };
80};
81
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]82&main_pmx0 {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]83 main_i2c0_pins_default: main-i2c0-default-pins {
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]84 pinctrl-single,pins = <
85 J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
86 J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
87 >;
88 };
89
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]90 main_mcan16_pins_default: main-mcan16-default-pins {
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]91 pinctrl-single,pins = <
92 J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
93 J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
94 >;
95 };
96};
97
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]98&wkup_i2c0 {
99 status = "okay";
100 pinctrl-names = "default";
101 pinctrl-0 = <&wkup_i2c0_pins_default>;
102 clock-frequency = <400000>;
103
104 eeprom@50 {
105 /* CAV24C256WE-GT3 */
106 compatible = "atmel,24c256";
107 reg = <0x50>;
108 };
109};
110
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]111&main_i2c0 {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]112 status = "okay";
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]113 pinctrl-names = "default";
114 pinctrl-0 = <&main_i2c0_pins_default>;
115 clock-frequency = <400000>;
116
117 exp_som: gpio@21 {
118 compatible = "ti,tca6408";
119 reg = <0x21>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
123 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
124 "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
125 "GPIO_LIN_EN", "CAN_STB";
126 };
127};
128
129&main_mcan16 {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]130 status = "okay";
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]131 pinctrl-0 = <&main_mcan16_pins_default>;
132 pinctrl-names = "default";
133 phys = <&transceiver0>;
134};
135
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]136&ospi0 {
137 status = "okay";
138 pinctrl-names = "default";
139 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]140
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]141 flash@0 {
142 compatible = "jedec,spi-nor";
143 reg = <0x0>;
144 spi-tx-bus-width = <8>;
145 spi-rx-bus-width = <8>;
146 spi-max-frequency = <25000000>;
147 cdns,tshsl-ns = <60>;
148 cdns,tsd2d-ns = <60>;
149 cdns,tchsh-ns = <60>;
150 cdns,tslch-ns = <60>;
151 cdns,read-delay = <4>;
152 };
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]153};