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git01.mediatek.com / filogic / uboot / 3181a8710675fd1e3cfb8b8279b2f21d551753da / . / arch / arm / dts / imx8mp-verdin-dev.dtsi
blob: bdfdd4c782f1d51ffe12ad92f4e1b13a8369d813 [file] [log] [blame]
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]6/ {
7 /* TODO: Audio Codec */
8
9 reg_eth2phy: regulator-eth2phy {
10 compatible = "regulator-fixed";
11 enable-active-high;
12 gpio = <&gpio_expander_21 4 GPIO_ACTIVE_HIGH>; /* ETH_PWR_EN */
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]13 off-on-delay-us = <500000>;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]14 regulator-max-microvolt = <3300000>;
15 regulator-min-microvolt = <3300000>;
16 regulator-name = "+V3.3_ETH";
17 startup-delay-us = <200000>;
18 vin-supply = <&reg_3p3v>;
19 };
20};
21
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]22&backlight {
23 power-supply = <&reg_3p3v>;
24};
25
26/* Verdin SPI_1 */
27&ecspi1 {
28 status = "okay";
29};
30
31/* EEPROM on display adapter boards */
32&eeprom_display_adapter {
33 status = "okay";
34};
35
36/* EEPROM on Verdin Development board */
37&eeprom_carrier_board {
38 status = "okay";
39};
40
41&eqos {
42 status = "okay";
43};
44
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]45&fec {
46 phy-supply = <&reg_eth2phy>;
47 status = "okay";
48};
49
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]50&flexcan1 {
51 status = "okay";
52};
53
54&flexcan2 {
55 status = "okay";
56};
57
58/* Verdin QSPI_1 */
59&flexspi {
60 status = "okay";
61};
62
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]63&gpio_expander_21 {
64 status = "okay";
65 vcc-supply = <&reg_1p8v>;
66};
67
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]68/* Current measurement into module VCC */
69&hwmon {
70 status = "okay";
71};
72
73&hwmon_temp {
74 vs-supply = <&reg_1p8v>;
75 status = "okay";
76};
77
78/* Verdin I2C_2_DSI */
79&i2c2 {
80 status = "okay";
81};
82
83&i2c3 {
84 status = "okay";
85};
86
87/* Verdin I2C_1 */
88&i2c4 {
89 status = "okay";
90
91 /* TODO: Audio Codec */
92};
93
94/* Verdin PCIE_1 */
95&pcie {
96 status = "okay";
97};
98
99&pcie_phy {
100 status = "okay";
101};
102
103/* Verdin PWM_1 */
104&pwm1 {
105 status = "okay";
106};
107
108/* Verdin PWM_2 */
109&pwm2 {
110 status = "okay";
111};
112
113/* Verdin PWM_3_DSI */
114&pwm3 {
115 status = "okay";
116};
117
118&reg_usdhc2_vmmc {
119 vin-supply = <&reg_3p3v>;
120};
121
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]122/* TODO: Verdin I2C_1 with Audio Codec */
123
124/* Verdin UART_1, connector X50 through RS485 transceiver */
125&uart1 {
126 linux,rs485-enabled-at-boot-time;
127 rs485-rts-active-low;
128 rs485-rx-during-tx;
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]129 status = "okay";
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]130};
131
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]132/* Verdin UART_2 */
133&uart2 {
134 status = "okay";
135};
136
137/* Verdin UART_3, used as the Linux Console */
138&uart3 {
139 status = "okay";
140};
141
142/* Verdin USB_1 */
143&usb3_0 {
144 status = "okay";
145};
146
147&usb3_phy0 {
148 status = "okay";
149};
150
151/* Verdin USB_2 */
152&usb3_1 {
153 fsl,permanently-attached;
154 status = "okay";
155};
156
157&usb3_phy1 {
158 status = "okay";
159};
160
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]161/* Limit frequency on dev board due to long traces and bad signal integrity */
162&usdhc2 {
163 max-frequency = <100000000>;
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]164 status = "okay";
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]165};