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git01.mediatek.com / filogic / uboot / 591b2ef7bc6474cbe480bc58fc1b992ef6e1a9b6 / . / arch / arm / dts / zynqmp-vpk120-revA.dts
blob: 66919f578e0213ff607b8afe3ec9088fe098f228 [file] [log] [blame]
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VPK120 RevA System Controller
4 *
5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20 model = "ZynqMP System Controller on VPK120 board RevA";
21 compatible = "xlnx,zynqmp-vpk120-revA",
22 "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
23
24 aliases {
25 ethernet0 = &gem0;
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 mmc0 = &sdhci0;
29 serial0 = &uart0;
30 serial1 = &dcc;
31 spi0 = &qspi;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 nvmem0 = &eeprom;
35 };
36
37 chosen {
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>;
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
49 autorepeat;
50 sw16 {
51 label = "sw16";
52 gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
53 linux,code = <BTN_MISC>;
54 wakeup-source;
55 autorepeat;
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
61 heartbeat-led { /* ds40 */
62 label = "heartbeat";
63 gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
67
68 si5332_0: si5332_0 { /* ps_ref_clk */
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <33333333>;
72 };
73
74 si5332_1: si5332_1 { /* clk0_sgmii */
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <33333333>; /* FIXME */
78 };
79
80 si5332_2: si5332_2 { /* clk1_usb */
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <27000000>;
84 };
85};
86
87&qspi { /* MIO 0-5 */
88 status = "okay";
89 flash@0 {
90 compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
91 #address-cells = <1>;
92 #size-cells = <1>;
93 reg = <0>;
94 spi-tx-bus-width = <4>;
95 spi-rx-bus-width = <4>;
96 spi-max-frequency = <108000000>;
97 partition@0 { /* for testing purpose */
98 label = "qspi";
99 reg = <0 0x4000000>;
100 };
101 };
102};
103
104&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
105 status = "okay";
106 non-removable;
107 disable-wp;
108 bus-width = <8>;
109 xlnx,mio-bank = <0>;
110};
111
112&uart0 { /* uart0 MIO38-39 */
113 status = "okay";
114 bootph-all;
115};
116
117&gem0 {
118 status = "okay";
119 phy-handle = <&phy0>;
120 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
121 is-internal-pcspma;
122 /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
123 /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
124 phy0: ethernet-phy@0 {
125 reg = <0>;
126 };
127};
128
129&gpio {
130 status = "okay";
131 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
132 "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
133 "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
134 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
135 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
136 "", "", "", "", "", /* 25 - 29 */
137 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
138 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
139 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
140 "", "", "", "", "", /* 45 - 49 */
141 "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
142 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
143 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
144 "", "", "", "", "", /* 65 - 69 */
145 "", "", "", "", "", /* 70 - 74 */
146 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
147 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
148 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
149 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
150 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
151 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
152 "", "", "", "", "", /* 100 - 104 */
153 "", "", "", "", "", /* 105 - 109 */
154 "", "", "", "", "", /* 110 - 114 */
155 "", "", "", "", "", /* 115 - 119 */
156 "", "", "", "", "", /* 120 - 124 */
157 "", "", "", "", "", /* 125 - 129 */
158 "", "", "", "", "", /* 130 - 134 */
159 "", "", "", "", "", /* 135 - 139 */
160 "", "", "", "", "", /* 140 - 144 */
161 "", "", "", "", "", /* 145 - 149 */
162 "", "", "", "", "", /* 150 - 154 */
163 "", "", "", "", "", /* 155 - 159 */
164 "", "", "", "", "", /* 160 - 164 */
165 "", "", "", "", "", /* 165 - 169 */
166 "", "", "", ""; /* 170 - 173 */
167};
168
169&i2c0 { /* MIO 34-35 - can't stay here */
170 status = "okay";
171 clock-frequency = <400000>;
172 pinctrl-names = "default", "gpio";
173 pinctrl-0 = <&pinctrl_i2c0_default>;
174 pinctrl-1 = <&pinctrl_i2c0_gpio>;
175 scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
176 sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
177
178 tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
179 compatible = "ti,tca6416";
180 reg = <0x20>;
181 gpio-controller; /* interrupt not connected */
182 #gpio-cells = <2>;
183 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */
184 "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
185 "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
186 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
187 };
188
189 i2c-mux@74 { /* u33 */
190 compatible = "nxp,pca9548";
191 #address-cells = <1>;
192 #size-cells = <0>;
193 reg = <0x74>;
194 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
195 pmbus_i2c: i2c@0 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 reg = <0>;
199 /* On connector J325 */
200 ir38060_41: regulator@41 { /* IR38060 - u259 */
201 compatible = "infineon,ir38060", "infineon,ir38064";
202 reg = <0x41>; /* i2c addr 0x11 */
203 };
204 ir38164_43: regulator@43 { /* IR38164 - u13 */
205 compatible = "infineon,ir38164";
206 reg = <0x43>; /* i2c addr 0x13 */
207 };
208 ir35221_45: pmic@46 { /* IR35221 - u152 */
209 compatible = "infineon,ir35221";
210 reg = <0x46>; /* PMBUS - 0x16 */
211 };
212 irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
213 compatible = "infineon,irps5401";
214 reg = <0x47>; /* i2c addr 0x17 */
215 };
216 ir38164_49: regulator@49 { /* IR38164 - u189 */
217 compatible = "infineon,ir38164";
218 reg = <0x49>; /* i2c addr 0x19 */
219 };
220 irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
221 compatible = "infineon,irps5401";
222 reg = <0x4c>; /* i2c addr 0x1c */
223 };
224 irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
225 compatible = "infineon,irps5401";
226 reg = <0x4d>; /* i2c addr 0x1c */
227 };
228 ir38164_4e: regulator@4e { /* IR38164 - u184 */
229 compatible = "infineon,ir38164";
230 reg = <0x4e>; /* i2c addr 0x1e */
231 };
232 ir38164_4f: regulator@4f { /* IR38164 - u187 */
233 compatible = "infineon,ir38164";
234 reg = <0x4f>; /* i2c addr 0x1f */
235 };
236 };
237 pmbus1_ina226_i2c: i2c@1 {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 reg = <1>;
241 /* FIXME check alerts coming to SC */
242 vccint: ina226@40 { /* u65 */
243 compatible = "ti,ina226";
244 reg = <0x40>;
245 shunt-resistor = <5000>;
246 };
247 vcc_soc: ina226@41 { /* u161 */
248 compatible = "ti,ina226";
249 reg = <0x41>;
250 shunt-resistor = <5000>;
251 };
252 vcc_pmc: ina226@42 { /* u163 */
253 compatible = "ti,ina226";
254 reg = <0x42>;
255 shunt-resistor = <5000>;
256 };
257 vcc_ram: ina226@43 { /* u5 */
258 compatible = "ti,ina226";
259 reg = <0x43>;
260 shunt-resistor = <5000>;
261 };
262 vcc_pslp: ina226@44 { /* u165 */
263 compatible = "ti,ina226";
264 reg = <0x44>;
265 shunt-resistor = <5000>;
266 };
267 vcc_psfp: ina226@45 { /* u164 */
268 compatible = "ti,ina226";
269 reg = <0x45>;
270 shunt-resistor = <5000>;
271 };
272 };
273 i2c@2 { /* NC */ /* FIXME maybe remove */
274 #address-cells = <1>;
275 #size-cells = <0>;
276 reg = <2>;
277 };
278 pmbus2_ina226_i2c: i2c@3 {
279 #address-cells = <1>;
280 #size-cells = <0>;
281 reg = <3>;
282 /* FIXME check alerts coming to SC */
283 vccaux: ina226@40 { /* u166 */
284 compatible = "ti,ina226";
285 reg = <0x40>;
286 shunt-resistor = <5000>;
287 };
288 vccaux_pmc: ina226@41 { /* u168 */
289 compatible = "ti,ina226";
290 reg = <0x41>;
291 shunt-resistor = <5000>;
292 };
293 mgtavcc: ina226@42 { /* u265 */
294 compatible = "ti,ina226";
295 reg = <0x42>;
296 shunt-resistor = <5000>;
297 };
298 vcc1v5: ina226@43 { /* u264 */
299 compatible = "ti,ina226";
300 reg = <0x43>;
301 shunt-resistor = <5000>;
302 };
303 vcco_mio: ina226@45 { /* u172 */
304 compatible = "ti,ina226";
305 reg = <0x45>;
306 shunt-resistor = <5000>;
307 };
308 mgtavtt: ina226@46 { /* u188 */
309 compatible = "ti,ina226";
310 reg = <0x46>;
311 shunt-resistor = <2000>;
312 };
313 vcco_502: ina226@47 { /* u174 */
314 compatible = "ti,ina226";
315 reg = <0x47>;
316 shunt-resistor = <5000>;
317 };
318 mgtvccaux: ina226@48 { /* u176 */
319 compatible = "ti,ina226";
320 reg = <0x48>;
321 shunt-resistor = <5000>;
322 };
323 vcc1v1_lp4: ina226@49 { /* u186 */
324 compatible = "ti,ina226";
325 reg = <0x49>;
326 shunt-resistor = <2000>;
327 };
328 vadj_fmc: ina226@4a { /* u184 */
329 compatible = "ti,ina226";
330 reg = <0x4a>;
331 shunt-resistor = <2000>;
332 };
333 lpdmgtyavcc: ina226@4b { /* u177 */
334 compatible = "ti,ina226";
335 reg = <0x4b>;
336 shunt-resistor = <5000>;
337 };
338 lpdmgtyavtt: ina226@4c { /* u260 */
339 compatible = "ti,ina226";
340 reg = <0x4c>;
341 shunt-resistor = <2000>;
342 };
343 lpdmgtyvccaux: ina226@4d { /* u234 */
344 compatible = "ti,ina226";
345 reg = <0x4d>;
346 shunt-resistor = <5000>;
347 };
348 };
349 i2c@4 { /* NC */
350 #address-cells = <1>;
351 #size-cells = <0>;
352 reg = <4>;
353 };
354 i2c@5 { /* NC */
355 #address-cells = <1>;
356 #size-cells = <0>;
357 reg = <5>;
358 };
359 user_si570: i2c@6 {
360 #address-cells = <1>;
361 #size-cells = <0>;
362 reg = <6>;
363 user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */
364 #clock-cells = <0>;
365 compatible = "silabs,si570";
366 reg = <0x5f>;
367 temperature-stability = <50>;
368 factory-fout = <100000000>;
369 clock-frequency = <100000000>;
370 clock-output-names = "fmc_si570";
371 };
372
373 };
374 /* 7 unused */
375 };
376};
377
378&i2c1 { /* i2c1 MIO 36-37 */
379 status = "okay";
380 clock-frequency = <400000>;
381 pinctrl-names = "default", "gpio";
382 pinctrl-0 = <&pinctrl_i2c1_default>;
383 pinctrl-1 = <&pinctrl_i2c1_gpio>;
384 scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
385 sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
386
387 i2c-mux@74 { /* u35 */
388 compatible = "nxp,pca9548";
389 #address-cells = <1>;
390 #size-cells = <0>;
391 reg = <0x74>;
392 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
393 ref_clk_i2c: i2c@0 {
394 #address-cells = <1>;
395 #size-cells = <0>;
396 reg = <0>;
397 /* Use for storing information about SC board */
398 eeprom: eeprom@54 { /* u34 - m24128 16kB */
399 compatible = "st,24c128", "atmel,24c128";
400 reg = <0x54>; /* & 0x5c */
401 };
402 ref_clk: clock-generator@5d { /* u32 */
403 #clock-cells = <0>;
404 compatible = "silabs,si570";
405 reg = <0x5d>;
406 temperature-stability = <50>;
407 factory-fout = <33333333>;
408 clock-frequency = <33333333>;
409 clock-output-names = "ref_clk";
410 silabs,skip-recall;
411 };
412 };
413 fmcp1_i2c: i2c@1 {
414 #address-cells = <1>;
415 #size-cells = <0>;
416 reg = <1>;
417 /* FIXME connection to Samtec J51C */
418 /* expected eeprom 0x50 SE cards */
419 };
420 i2c@2 { /* NC - FIXME */
421 #address-cells = <1>;
422 #size-cells = <0>;
423 reg = <2>;
424 };
425 lpddr4_si570_clk3_i2c: i2c@3 {
426 #address-cells = <1>;
427 #size-cells = <0>;
428 reg = <3>;
429 lpddr4_clk3: clock-generator@60 { /* u4 */
430 #clock-cells = <0>;
431 compatible = "silabs,si570";
432 reg = <0x60>;
433 temperature-stability = <50>;
434 factory-fout = <200000000>;
435 clock-frequency = <200000000>;
436 clock-output-names = "lpddr4_clk3";
437 };
438 };
439 lpddr4_si570_clk2_i2c: i2c@4 {
440 #address-cells = <1>;
441 #size-cells = <0>;
442 reg = <4>;
443 lpddr4_clk2: clock-generator@60 { /* u3 */
444 #clock-cells = <0>;
445 compatible = "silabs,si570";
446 reg = <0x60>;
447 temperature-stability = <50>;
448 factory-fout = <200000000>;
449 clock-frequency = <200000000>;
450 clock-output-names = "lpddr4_clk2";
451 };
452 };
453 lpddr4_si570_clk1_i2c: i2c@5 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 reg = <5>;
457 lpddr4_clk1: clock-generator@60 { /* u248 */
458 #clock-cells = <0>;
459 compatible = "silabs,si570";
460 reg = <0x60>;
461 temperature-stability = <50>;
462 factory-fout = <200000000>;
463 clock-frequency = <200000000>;
464 clock-output-names = "lpddr4_clk1";
465 };
466 };
467 qsfpdd_i2c: i2c@6 {
468 #address-cells = <1>;
469 #size-cells = <0>;
470 reg = <6>;
471 /* J1/J2 connectors */
472 };
473 idt8a34001_i2c: i2c@7 {
474 #address-cells = <1>;
475 #size-cells = <0>;
476 reg = <7>;
477 /* Via J310 connector */
478 idt_8a34001: phc@5b {
479 compatible = "idt,8a34001"; /* u219B */
480 reg = <0x5b>; /* FIXME not in schematics */
481 };
482 };
483 };
484};
485
486&usb0 { /* MIO52 - MIO63 */
487 status = "okay";
488 phy-names = "usb3-phy";
489 phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
490};
491
492&psgtr {
493 status = "okay";
494 /* sgmii, usb3 */
495 clocks = <&si5332_1>, <&si5332_2>;
496 clock-names = "ref0", "ref1";
497};
498
499&dwc3_0 {
500 status = "okay";
501 dr_mode = "peripheral";
502 snps,dis_u2_susphy_quirk;
503 snps,dis_u3_susphy_quirk;
504 maximum-speed = "super-speed";
505};
506
507&xilinx_ams {
508 status = "okay";
509};
510
511&ams_ps {
512 status = "okay";
513};
514
515&ams_pl {
516 status = "okay";
517};
518
519&pinctrl0 {
520 status = "okay";
521 pinctrl_i2c0_default: i2c0-default {
522 mux {
523 groups = "i2c0_8_grp";
524 function = "i2c0";
525 };
526
527 conf {
528 groups = "i2c0_8_grp";
529 bias-pull-up;
530 slew-rate = <SLEW_RATE_SLOW>;
531 power-source = <IO_STANDARD_LVCMOS18>;
532 };
533 };
534
535 pinctrl_i2c0_gpio: i2c0-gpio {
536 mux {
537 groups = "gpio0_34_grp", "gpio0_35_grp";
538 function = "gpio0";
539 };
540
541 conf {
542 groups = "gpio0_34_grp", "gpio0_35_grp";
543 slew-rate = <SLEW_RATE_SLOW>;
544 power-source = <IO_STANDARD_LVCMOS18>;
545 };
546 };
547
548 pinctrl_i2c1_default: i2c1-default {
549 mux {
550 groups = "i2c1_9_grp";
551 function = "i2c1";
552 };
553
554 conf {
555 groups = "i2c1_9_grp";
556 bias-pull-up;
557 slew-rate = <SLEW_RATE_SLOW>;
558 power-source = <IO_STANDARD_LVCMOS18>;
559 };
560 };
561
562 pinctrl_i2c1_gpio: i2c1-gpio {
563 mux {
564 groups = "gpio0_36_grp", "gpio0_37_grp";
565 function = "gpio0";
566 };
567
568 conf {
569 groups = "gpio0_36_grp", "gpio0_37_grp";
570 slew-rate = <SLEW_RATE_SLOW>;
571 power-source = <IO_STANDARD_LVCMOS18>;
572 };
573 };
574};