blob: e45f0961b242cdd92c344bcd186583dc80131f5b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Thierry Reding7db387c2014-12-09 22:25:08 -07002/*
3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
Thierry Reding7db387c2014-12-09 22:25:08 -07004 */
5
6#include <common.h>
7#include <errno.h>
8
9#include <asm/io.h>
10#include <asm/types.h>
Stephen Warren01d9ab12018-06-22 13:02:27 -060011
Thierry Reding7db387c2014-12-09 22:25:08 -070012#include <asm/arch/powergate.h>
13#include <asm/arch/tegra.h>
14
15#define PWRGATE_TOGGLE 0x30
16#define PWRGATE_TOGGLE_START (1 << 8)
17
18#define REMOVE_CLAMPING 0x34
19
20#define PWRGATE_STATUS 0x38
21
22static int tegra_powergate_set(enum tegra_powergate id, bool state)
23{
24 u32 value, mask = state ? (1 << id) : 0, old_mask;
25 unsigned long start, timeout = 25;
26
27 value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
28 old_mask = value & (1 << id);
29
30 if (mask == old_mask)
31 return 0;
32
33 writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
34
35 start = get_timer(0);
36
37 while (get_timer(start) < timeout) {
38 value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
39 if ((value & (1 << id)) == mask)
40 return 0;
41 }
42
43 return -ETIMEDOUT;
44}
45
Jan Kiszkaaf0d2292015-04-21 07:18:33 +020046int tegra_powergate_power_on(enum tegra_powergate id)
Thierry Reding7db387c2014-12-09 22:25:08 -070047{
48 return tegra_powergate_set(id, true);
49}
50
51int tegra_powergate_power_off(enum tegra_powergate id)
52{
53 return tegra_powergate_set(id, false);
54}
55
56static int tegra_powergate_remove_clamping(enum tegra_powergate id)
57{
58 unsigned long value;
59
60 /*
61 * The REMOVE_CLAMPING register has the bits for the PCIE and VDEC
62 * partitions reversed. This was originally introduced on Tegra20 but
63 * has since been carried forward for backwards-compatibility.
64 */
65 if (id == TEGRA_POWERGATE_VDEC)
66 value = 1 << TEGRA_POWERGATE_PCIE;
67 else if (id == TEGRA_POWERGATE_PCIE)
68 value = 1 << TEGRA_POWERGATE_VDEC;
69 else
70 value = 1 << id;
71
72 writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
73
74 return 0;
75}
76
77int tegra_powergate_sequence_power_up(enum tegra_powergate id,
78 enum periph_id periph)
79{
80 int err;
81
Thierry Reding7db387c2014-12-09 22:25:08 -070082 reset_set_enable(periph, 1);
83
84 err = tegra_powergate_power_on(id);
85 if (err < 0)
86 return err;
87
88 clock_enable(periph);
89
90 udelay(10);
91
92 err = tegra_powergate_remove_clamping(id);
93 if (err < 0)
94 return err;
95
96 udelay(10);
97
98 reset_set_enable(periph, 0);
99
100 return 0;
101}