Patrick Delaunay | d65291b | 2019-03-11 11:13:15 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
| 4 | * |
| 5 | * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander |
| 6 | * based on Linux driver : pinctrl/pinctrl-stmfx.c |
| 7 | */ |
| 8 | #include <common.h> |
| 9 | #include <dm.h> |
| 10 | #include <i2c.h> |
| 11 | #include <asm/gpio.h> |
| 12 | #include <dm/device.h> |
| 13 | #include <dm/device-internal.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 14 | #include <dm/device_compat.h> |
Patrick Delaunay | d65291b | 2019-03-11 11:13:15 +0100 | [diff] [blame] | 15 | #include <dm/lists.h> |
| 16 | #include <dm/pinctrl.h> |
| 17 | #include <linux/bitfield.h> |
| 18 | #include <power/regulator.h> |
| 19 | |
| 20 | /* STMFX pins = GPIO[15:0] + aGPIO[7:0] */ |
| 21 | #define STMFX_MAX_GPIO 16 |
| 22 | #define STMFX_MAX_AGPIO 8 |
| 23 | |
| 24 | /* General */ |
| 25 | #define STMFX_REG_CHIP_ID 0x00 /* R */ |
| 26 | #define STMFX_REG_FW_VERSION_MSB 0x01 /* R */ |
| 27 | #define STMFX_REG_FW_VERSION_LSB 0x02 /* R */ |
| 28 | #define STMFX_REG_SYS_CTRL 0x40 /* RW */ |
| 29 | |
| 30 | /* MFX boot time is around 10ms, so after reset, we have to wait this delay */ |
| 31 | #define STMFX_BOOT_TIME_MS 10 |
| 32 | |
| 33 | /* GPIOs expander */ |
| 34 | /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */ |
| 35 | #define STMFX_REG_GPIO_STATE 0x10 /* R */ |
| 36 | /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */ |
| 37 | #define STMFX_REG_GPIO_DIR 0x60 /* RW */ |
| 38 | /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */ |
| 39 | #define STMFX_REG_GPIO_TYPE 0x64 /* RW */ |
| 40 | /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */ |
| 41 | #define STMFX_REG_GPIO_PUPD 0x68 /* RW */ |
| 42 | /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */ |
| 43 | #define STMFX_REG_GPO_SET 0x6C /* RW */ |
| 44 | /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */ |
| 45 | #define STMFX_REG_GPO_CLR 0x70 /* RW */ |
| 46 | |
| 47 | /* STMFX_REG_CHIP_ID bitfields */ |
| 48 | #define STMFX_REG_CHIP_ID_MASK GENMASK(7, 0) |
| 49 | |
| 50 | /* STMFX_REG_SYS_CTRL bitfields */ |
| 51 | #define STMFX_REG_SYS_CTRL_GPIO_EN BIT(0) |
| 52 | #define STMFX_REG_SYS_CTRL_ALTGPIO_EN BIT(3) |
| 53 | #define STMFX_REG_SYS_CTRL_SWRST BIT(7) |
| 54 | |
| 55 | #define NR_GPIO_REGS 3 |
| 56 | #define NR_GPIOS_PER_REG 8 |
| 57 | #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG) |
| 58 | #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG) |
| 59 | #define get_mask(offset) (BIT(get_shift(offset))) |
| 60 | |
| 61 | struct stmfx_pinctrl { |
| 62 | struct udevice *gpio; |
| 63 | }; |
| 64 | |
| 65 | static int stmfx_read(struct udevice *dev, uint offset) |
| 66 | { |
| 67 | return dm_i2c_reg_read(dev_get_parent(dev), offset); |
| 68 | } |
| 69 | |
| 70 | static int stmfx_write(struct udevice *dev, uint offset, unsigned int val) |
| 71 | { |
| 72 | return dm_i2c_reg_write(dev_get_parent(dev), offset, val); |
| 73 | } |
| 74 | |
| 75 | static int stmfx_gpio_get(struct udevice *dev, unsigned int offset) |
| 76 | { |
| 77 | u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset); |
| 78 | u32 mask = get_mask(offset); |
| 79 | int ret; |
| 80 | |
| 81 | ret = stmfx_read(dev, reg); |
| 82 | |
| 83 | return ret < 0 ? ret : !!(ret & mask); |
| 84 | } |
| 85 | |
| 86 | static int stmfx_gpio_set(struct udevice *dev, unsigned int offset, int value) |
| 87 | { |
| 88 | u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; |
| 89 | u32 mask = get_mask(offset); |
| 90 | |
| 91 | return stmfx_write(dev, reg + get_reg(offset), mask); |
| 92 | } |
| 93 | |
| 94 | static int stmfx_gpio_get_function(struct udevice *dev, unsigned int offset) |
| 95 | { |
| 96 | u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); |
| 97 | u32 mask = get_mask(offset); |
| 98 | int ret; |
| 99 | |
| 100 | ret = stmfx_read(dev, reg); |
| 101 | |
| 102 | if (ret < 0) |
| 103 | return ret; |
| 104 | /* On stmfx, gpio pins direction is (0)input, (1)output. */ |
| 105 | |
| 106 | return ret & mask ? GPIOF_OUTPUT : GPIOF_INPUT; |
| 107 | } |
| 108 | |
| 109 | static int stmfx_gpio_direction_input(struct udevice *dev, unsigned int offset) |
| 110 | { |
| 111 | u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); |
| 112 | u32 mask = get_mask(offset); |
| 113 | int ret; |
| 114 | |
| 115 | ret = stmfx_read(dev, reg); |
| 116 | if (ret < 0) |
| 117 | return ret; |
| 118 | |
| 119 | ret &= ~mask; |
| 120 | |
| 121 | return stmfx_write(dev, reg, ret & ~mask); |
| 122 | } |
| 123 | |
| 124 | static int stmfx_gpio_direction_output(struct udevice *dev, |
| 125 | unsigned int offset, int value) |
| 126 | { |
| 127 | u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); |
| 128 | u32 mask = get_mask(offset); |
| 129 | int ret; |
| 130 | |
| 131 | ret = stmfx_gpio_set(dev, offset, value); |
| 132 | if (ret < 0) |
| 133 | return ret; |
| 134 | |
| 135 | ret = stmfx_read(dev, reg); |
| 136 | if (ret < 0) |
| 137 | return ret; |
| 138 | |
| 139 | return stmfx_write(dev, reg, ret | mask); |
| 140 | } |
| 141 | |
| 142 | static int stmfx_gpio_probe(struct udevice *dev) |
| 143 | { |
| 144 | struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
| 145 | struct ofnode_phandle_args args; |
| 146 | u8 sys_ctrl; |
| 147 | |
| 148 | uc_priv->bank_name = "stmfx"; |
| 149 | uc_priv->gpio_count = STMFX_MAX_GPIO + STMFX_MAX_AGPIO; |
| 150 | if (!dev_read_phandle_with_args(dev, "gpio-ranges", |
| 151 | NULL, 3, 0, &args)) { |
| 152 | uc_priv->gpio_count = args.args[2]; |
| 153 | } |
| 154 | |
| 155 | /* enable GPIO function */ |
| 156 | sys_ctrl = STMFX_REG_SYS_CTRL_GPIO_EN; |
| 157 | if (uc_priv->gpio_count > STMFX_MAX_GPIO) |
| 158 | sys_ctrl |= STMFX_REG_SYS_CTRL_ALTGPIO_EN; |
| 159 | stmfx_write(dev, STMFX_REG_SYS_CTRL, sys_ctrl); |
| 160 | |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | static const struct dm_gpio_ops stmfx_gpio_ops = { |
| 165 | .set_value = stmfx_gpio_set, |
| 166 | .get_value = stmfx_gpio_get, |
| 167 | .get_function = stmfx_gpio_get_function, |
| 168 | .direction_input = stmfx_gpio_direction_input, |
| 169 | .direction_output = stmfx_gpio_direction_output, |
| 170 | }; |
| 171 | |
| 172 | U_BOOT_DRIVER(stmfx_gpio) = { |
| 173 | .name = "stmfx-gpio", |
| 174 | .id = UCLASS_GPIO, |
| 175 | .probe = stmfx_gpio_probe, |
| 176 | .ops = &stmfx_gpio_ops, |
| 177 | }; |
| 178 | |
| 179 | #if CONFIG_IS_ENABLED(PINCONF) |
| 180 | static const struct pinconf_param stmfx_pinctrl_conf_params[] = { |
| 181 | { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, |
| 182 | { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 0 }, |
| 183 | { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 0 }, |
| 184 | { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 0 }, |
| 185 | { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, |
| 186 | { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, |
| 187 | { "output-high", PIN_CONFIG_OUTPUT, 1 }, |
| 188 | { "output-low", PIN_CONFIG_OUTPUT, 0 }, |
| 189 | }; |
| 190 | |
| 191 | static int stmfx_pinctrl_set_pupd(struct udevice *dev, |
| 192 | unsigned int pin, u32 pupd) |
| 193 | { |
| 194 | u8 reg = STMFX_REG_GPIO_PUPD + get_reg(pin); |
| 195 | u32 mask = get_mask(pin); |
| 196 | int ret; |
| 197 | |
| 198 | ret = stmfx_read(dev, reg); |
| 199 | if (ret < 0) |
| 200 | return ret; |
| 201 | ret = (ret & ~mask) | (pupd ? mask : 0); |
| 202 | |
| 203 | return stmfx_write(dev, reg, ret); |
| 204 | } |
| 205 | |
| 206 | static int stmfx_pinctrl_set_type(struct udevice *dev, |
| 207 | unsigned int pin, u32 type) |
| 208 | { |
| 209 | u8 reg = STMFX_REG_GPIO_TYPE + get_reg(pin); |
| 210 | u32 mask = get_mask(pin); |
| 211 | int ret; |
| 212 | |
| 213 | ret = stmfx_read(dev, reg); |
| 214 | if (ret < 0) |
| 215 | return ret; |
| 216 | ret = (ret & ~mask) | (type ? mask : 0); |
| 217 | |
| 218 | return stmfx_write(dev, reg, ret); |
| 219 | } |
| 220 | |
| 221 | static int stmfx_pinctrl_conf_set(struct udevice *dev, unsigned int pin, |
| 222 | unsigned int param, unsigned int arg) |
| 223 | { |
| 224 | int ret, dir; |
| 225 | struct stmfx_pinctrl *plat = dev_get_platdata(dev); |
| 226 | |
| 227 | dir = stmfx_gpio_get_function(plat->gpio, pin); |
| 228 | |
| 229 | if (dir < 0) |
| 230 | return dir; |
| 231 | |
| 232 | switch (param) { |
| 233 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: |
| 234 | case PIN_CONFIG_BIAS_DISABLE: |
Patrick Delaunay | 461a9cd | 2019-07-30 19:16:11 +0200 | [diff] [blame] | 235 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
| 236 | ret = stmfx_pinctrl_set_type(dev, pin, 0); |
| 237 | break; |
Patrick Delaunay | d65291b | 2019-03-11 11:13:15 +0100 | [diff] [blame] | 238 | case PIN_CONFIG_BIAS_PULL_DOWN: |
Patrick Delaunay | 461a9cd | 2019-07-30 19:16:11 +0200 | [diff] [blame] | 239 | ret = stmfx_pinctrl_set_type(dev, pin, 1); |
| 240 | if (ret) |
| 241 | return ret; |
Patrick Delaunay | d65291b | 2019-03-11 11:13:15 +0100 | [diff] [blame] | 242 | ret = stmfx_pinctrl_set_pupd(dev, pin, 0); |
| 243 | break; |
| 244 | case PIN_CONFIG_BIAS_PULL_UP: |
Patrick Delaunay | 461a9cd | 2019-07-30 19:16:11 +0200 | [diff] [blame] | 245 | ret = stmfx_pinctrl_set_type(dev, pin, 1); |
| 246 | if (ret) |
| 247 | return ret; |
Patrick Delaunay | d65291b | 2019-03-11 11:13:15 +0100 | [diff] [blame] | 248 | ret = stmfx_pinctrl_set_pupd(dev, pin, 1); |
| 249 | break; |
| 250 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
Patrick Delaunay | 461a9cd | 2019-07-30 19:16:11 +0200 | [diff] [blame] | 251 | ret = stmfx_pinctrl_set_type(dev, pin, 1); |
Patrick Delaunay | d65291b | 2019-03-11 11:13:15 +0100 | [diff] [blame] | 252 | break; |
| 253 | case PIN_CONFIG_OUTPUT: |
| 254 | ret = stmfx_gpio_direction_output(plat->gpio, pin, arg); |
| 255 | break; |
| 256 | default: |
| 257 | return -ENOTSUPP; |
| 258 | } |
| 259 | |
| 260 | return ret; |
| 261 | } |
| 262 | #endif |
| 263 | |
| 264 | static int stmfx_pinctrl_get_pins_count(struct udevice *dev) |
| 265 | { |
| 266 | struct stmfx_pinctrl *plat = dev_get_platdata(dev); |
| 267 | struct gpio_dev_priv *uc_priv; |
| 268 | |
| 269 | uc_priv = dev_get_uclass_priv(plat->gpio); |
| 270 | |
| 271 | return uc_priv->gpio_count; |
| 272 | } |
| 273 | |
| 274 | /* |
| 275 | * STMFX pins[15:0] are called "gpio[15:0]" |
| 276 | * and STMFX pins[23:16] are called "agpio[7:0]" |
| 277 | */ |
| 278 | #define MAX_PIN_NAME_LEN 7 |
| 279 | static char pin_name[MAX_PIN_NAME_LEN]; |
| 280 | static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev, |
| 281 | unsigned int selector) |
| 282 | { |
| 283 | if (selector < STMFX_MAX_GPIO) |
| 284 | snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); |
| 285 | else |
| 286 | snprintf(pin_name, MAX_PIN_NAME_LEN, "agpio%u", selector - 16); |
| 287 | return pin_name; |
| 288 | } |
| 289 | |
| 290 | static int stmfx_pinctrl_get_pin_muxing(struct udevice *dev, |
| 291 | unsigned int selector, |
| 292 | char *buf, int size) |
| 293 | { |
| 294 | struct stmfx_pinctrl *plat = dev_get_platdata(dev); |
| 295 | int func; |
| 296 | |
| 297 | func = stmfx_gpio_get_function(plat->gpio, selector); |
| 298 | if (func < 0) |
| 299 | return func; |
| 300 | |
| 301 | snprintf(buf, size, "%s", func == GPIOF_INPUT ? "input" : "output"); |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | static int stmfx_pinctrl_bind(struct udevice *dev) |
| 307 | { |
| 308 | struct stmfx_pinctrl *plat = dev_get_platdata(dev); |
| 309 | |
| 310 | return device_bind_driver_to_node(dev->parent, |
| 311 | "stmfx-gpio", "stmfx-gpio", |
| 312 | dev_ofnode(dev), &plat->gpio); |
| 313 | }; |
| 314 | |
| 315 | static int stmfx_pinctrl_probe(struct udevice *dev) |
| 316 | { |
| 317 | struct stmfx_pinctrl *plat = dev_get_platdata(dev); |
| 318 | |
| 319 | return device_probe(plat->gpio); |
| 320 | }; |
| 321 | |
| 322 | const struct pinctrl_ops stmfx_pinctrl_ops = { |
| 323 | .get_pins_count = stmfx_pinctrl_get_pins_count, |
| 324 | .get_pin_name = stmfx_pinctrl_get_pin_name, |
| 325 | .set_state = pinctrl_generic_set_state, |
| 326 | .get_pin_muxing = stmfx_pinctrl_get_pin_muxing, |
| 327 | #if CONFIG_IS_ENABLED(PINCONF) |
| 328 | .pinconf_set = stmfx_pinctrl_conf_set, |
| 329 | .pinconf_num_params = ARRAY_SIZE(stmfx_pinctrl_conf_params), |
| 330 | .pinconf_params = stmfx_pinctrl_conf_params, |
| 331 | #endif |
| 332 | }; |
| 333 | |
| 334 | static const struct udevice_id stmfx_pinctrl_match[] = { |
| 335 | { .compatible = "st,stmfx-0300-pinctrl", }, |
| 336 | }; |
| 337 | |
| 338 | U_BOOT_DRIVER(stmfx_pinctrl) = { |
| 339 | .name = "stmfx-pinctrl", |
| 340 | .id = UCLASS_PINCTRL, |
| 341 | .of_match = of_match_ptr(stmfx_pinctrl_match), |
| 342 | .bind = stmfx_pinctrl_bind, |
| 343 | .probe = stmfx_pinctrl_probe, |
| 344 | .ops = &stmfx_pinctrl_ops, |
| 345 | .platdata_auto_alloc_size = sizeof(struct stmfx_pinctrl), |
| 346 | }; |
| 347 | |
| 348 | static int stmfx_chip_init(struct udevice *dev) |
| 349 | { |
| 350 | u8 id; |
| 351 | u8 version[2]; |
| 352 | int ret; |
| 353 | struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); |
| 354 | |
Patrick Delaunay | e4c076f | 2020-01-28 10:44:14 +0100 | [diff] [blame] | 355 | ret = dm_i2c_reg_read(dev, STMFX_REG_CHIP_ID); |
| 356 | if (ret < 0) { |
| 357 | dev_err(dev, "error reading chip id: %d\n", ret); |
Patrick Delaunay | d65291b | 2019-03-11 11:13:15 +0100 | [diff] [blame] | 358 | return ret; |
| 359 | } |
Patrick Delaunay | e4c076f | 2020-01-28 10:44:14 +0100 | [diff] [blame] | 360 | id = (u8)ret; |
Patrick Delaunay | d65291b | 2019-03-11 11:13:15 +0100 | [diff] [blame] | 361 | /* |
| 362 | * Check that ID is the complement of the I2C address: |
| 363 | * STMFX I2C address follows the 7-bit format (MSB), that's why |
| 364 | * client->addr is shifted. |
| 365 | * |
| 366 | * STMFX_I2C_ADDR| STMFX | Linux |
| 367 | * input pin | I2C device address | I2C device address |
| 368 | *--------------------------------------------------------- |
| 369 | * 0 | b: 1000 010x h:0x84 | 0x42 |
| 370 | * 1 | b: 1000 011x h:0x86 | 0x43 |
| 371 | */ |
| 372 | if (FIELD_GET(STMFX_REG_CHIP_ID_MASK, ~id) != (chip->chip_addr << 1)) { |
| 373 | dev_err(dev, "unknown chip id: %#x\n", id); |
| 374 | return -EINVAL; |
| 375 | } |
| 376 | |
| 377 | ret = dm_i2c_read(dev, STMFX_REG_FW_VERSION_MSB, |
| 378 | version, sizeof(version)); |
| 379 | if (ret) { |
| 380 | dev_err(dev, "error reading fw version: %d\n", ret); |
| 381 | return ret; |
| 382 | } |
| 383 | |
| 384 | dev_info(dev, "STMFX id: %#x, fw version: %x.%02x\n", |
| 385 | id, version[0], version[1]); |
| 386 | |
| 387 | ret = dm_i2c_reg_read(dev, STMFX_REG_SYS_CTRL); |
| 388 | |
| 389 | if (ret < 0) |
| 390 | return ret; |
| 391 | |
| 392 | ret = dm_i2c_reg_write(dev, STMFX_REG_SYS_CTRL, |
| 393 | ret | STMFX_REG_SYS_CTRL_SWRST); |
| 394 | if (ret) |
| 395 | return ret; |
| 396 | |
| 397 | mdelay(STMFX_BOOT_TIME_MS); |
| 398 | |
| 399 | return ret; |
| 400 | } |
| 401 | |
| 402 | static int stmfx_probe(struct udevice *dev) |
| 403 | { |
| 404 | struct udevice *vdd; |
| 405 | int ret; |
| 406 | |
| 407 | ret = device_get_supply_regulator(dev, "vdd-supply", &vdd); |
| 408 | if (ret && ret != -ENOENT) { |
| 409 | dev_err(dev, "vdd regulator error:%d\n", ret); |
| 410 | return ret; |
| 411 | } |
| 412 | if (!ret) { |
| 413 | ret = regulator_set_enable(vdd, true); |
| 414 | if (ret) { |
| 415 | dev_err(dev, "vdd enable failed: %d\n", ret); |
| 416 | return ret; |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | return stmfx_chip_init(dev); |
| 421 | } |
| 422 | |
| 423 | static const struct udevice_id stmfx_match[] = { |
| 424 | { .compatible = "st,stmfx-0300", }, |
| 425 | }; |
| 426 | |
| 427 | U_BOOT_DRIVER(stmfx) = { |
| 428 | .name = "stmfx", |
| 429 | .id = UCLASS_I2C_GENERIC, |
| 430 | .of_match = of_match_ptr(stmfx_match), |
| 431 | .probe = stmfx_probe, |
| 432 | .bind = dm_scan_fdt_dev, |
| 433 | }; |