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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Peng Fanb11a7342018-01-10 13:20:20 +08002/*
3 * Copyright 2017 NXP
Peng Fanb11a7342018-01-10 13:20:20 +08004 */
5
Peng Fan39945c12018-11-20 10:19:25 +00006#ifndef __ASM_ARCH_IMX8M_REGS_H__
7#define __ASM_ARCH_IMX8M_REGS_H__
Peng Fanb11a7342018-01-10 13:20:20 +08008
Peng Fan00565bf2019-05-09 08:33:55 +00009#define ARCH_MXC
10
Peng Fanb11a7342018-01-10 13:20:20 +080011#include <asm/mach-imx/regs-lcdif.h>
12
13#define ROM_VERSION_A0 0x800
14#define ROM_VERSION_B0 0x83C
15
Peng Fanc627b302019-08-27 06:25:10 +000016#define M4_BOOTROM_BASE_ADDR 0x007E0000
Peng Fanb11a7342018-01-10 13:20:20 +080017
Peng Fanb11a7342018-01-10 13:20:20 +080018#define GPIO1_BASE_ADDR 0X30200000
19#define GPIO2_BASE_ADDR 0x30210000
20#define GPIO3_BASE_ADDR 0x30220000
21#define GPIO4_BASE_ADDR 0x30230000
22#define GPIO5_BASE_ADDR 0x30240000
Peng Fanb11a7342018-01-10 13:20:20 +080023#define WDOG1_BASE_ADDR 0x30280000
24#define WDOG2_BASE_ADDR 0x30290000
25#define WDOG3_BASE_ADDR 0x302A0000
Peng Fanb11a7342018-01-10 13:20:20 +080026#define LCDIF_BASE_ADDR 0x30320000
27#define IOMUXC_BASE_ADDR 0x30330000
28#define IOMUXC_GPR_BASE_ADDR 0x30340000
29#define OCOTP_BASE_ADDR 0x30350000
30#define ANATOP_BASE_ADDR 0x30360000
Peng Fanb11a7342018-01-10 13:20:20 +080031#define CCM_BASE_ADDR 0x30380000
32#define SRC_BASE_ADDR 0x30390000
33#define GPC_BASE_ADDR 0x303A0000
Peng Fanb11a7342018-01-10 13:20:20 +080034
Peng Fanb11a7342018-01-10 13:20:20 +080035#define SYSCNT_RD_BASE_ADDR 0x306A0000
36#define SYSCNT_CMP_BASE_ADDR 0x306B0000
37#define SYSCNT_CTRL_BASE_ADDR 0x306C0000
Peng Fanb11a7342018-01-10 13:20:20 +080038
Peng Fanb11a7342018-01-10 13:20:20 +080039#define UART1_BASE_ADDR 0x30860000
40#define UART3_BASE_ADDR 0x30880000
41#define UART2_BASE_ADDR 0x30890000
Peng Fanb11a7342018-01-10 13:20:20 +080042#define I2C1_BASE_ADDR 0x30A20000
43#define I2C2_BASE_ADDR 0x30A30000
44#define I2C3_BASE_ADDR 0x30A40000
45#define I2C4_BASE_ADDR 0x30A50000
46#define UART4_BASE_ADDR 0x30A60000
Peng Fanb11a7342018-01-10 13:20:20 +080047#define USDHC1_BASE_ADDR 0x30B40000
48#define USDHC2_BASE_ADDR 0x30B50000
Peng Fanb11a7342018-01-10 13:20:20 +080049
Peng Fanb11a7342018-01-10 13:20:20 +080050#define TZASC_BASE_ADDR 0x32F80000
Peng Fanb11a7342018-01-10 13:20:20 +080051
52#define MXS_LCDIF_BASE LCDIF_BASE_ADDR
53
54#define SRC_IPS_BASE_ADDR 0x30390000
55#define SRC_DDRC_RCR_ADDR 0x30391000
56#define SRC_DDRC2_RCR_ADDR 0x30391004
57
58#define DDRC_DDR_SS_GPR0 0x3d000000
59#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
60#define DDR_CSD1_BASE_ADDR 0x40000000
61
62#if !defined(__ASSEMBLY__)
63#include <asm/types.h>
64#include <linux/bitops.h>
65#include <stdbool.h>
66
67#define GPR_TZASC_EN BIT(0)
68#define GPR_TZASC_EN_LOCK BIT(16)
69
70#define SRC_SCR_M4_ENABLE_OFFSET 3
71#define SRC_SCR_M4_ENABLE_MASK BIT(3)
72#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
73#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
74#define SRC_DDR1_ENABLE_MASK 0x8F000000UL
75#define SRC_DDR2_ENABLE_MASK 0x8F000000UL
76#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
77#define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
78#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
79#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
80
81struct iomuxc_gpr_base_regs {
82 u32 gpr[47];
83};
84
85struct ocotp_regs {
86 u32 ctrl;
87 u32 ctrl_set;
88 u32 ctrl_clr;
89 u32 ctrl_tog;
90 u32 timing;
91 u32 rsvd0[3];
92 u32 data;
93 u32 rsvd1[3];
94 u32 read_ctrl;
95 u32 rsvd2[3];
96 u32 read_fuse_data;
97 u32 rsvd3[3];
98 u32 sw_sticky;
99 u32 rsvd4[3];
100 u32 scs;
101 u32 scs_set;
102 u32 scs_clr;
103 u32 scs_tog;
104 u32 crc_addr;
105 u32 rsvd5[3];
106 u32 crc_value;
107 u32 rsvd6[3];
108 u32 version;
109 u32 rsvd7[0xdb];
110
111 /* fuse banks */
112 struct fuse_bank {
113 u32 fuse_regs[0x10];
114 } bank[0];
115};
116
117struct fuse_bank0_regs {
118 u32 lock;
119 u32 rsvd0[3];
120 u32 uid_low;
121 u32 rsvd1[3];
122 u32 uid_high;
123 u32 rsvd2[7];
124};
125
126struct fuse_bank1_regs {
127 u32 tester3;
128 u32 rsvd0[3];
129 u32 tester4;
130 u32 rsvd1[3];
131 u32 tester5;
132 u32 rsvd2[3];
133 u32 cfg0;
134 u32 rsvd3[3];
135};
136
137struct anamix_pll {
138 u32 audio_pll1_cfg0;
139 u32 audio_pll1_cfg1;
140 u32 audio_pll2_cfg0;
141 u32 audio_pll2_cfg1;
142 u32 video_pll_cfg0;
143 u32 video_pll_cfg1;
144 u32 gpu_pll_cfg0;
145 u32 gpu_pll_cfg1;
146 u32 vpu_pll_cfg0;
147 u32 vpu_pll_cfg1;
148 u32 arm_pll_cfg0;
149 u32 arm_pll_cfg1;
150 u32 sys_pll1_cfg0;
151 u32 sys_pll1_cfg1;
152 u32 sys_pll1_cfg2;
153 u32 sys_pll2_cfg0;
154 u32 sys_pll2_cfg1;
155 u32 sys_pll2_cfg2;
156 u32 sys_pll3_cfg0;
157 u32 sys_pll3_cfg1;
158 u32 sys_pll3_cfg2;
159 u32 video_pll2_cfg0;
160 u32 video_pll2_cfg1;
161 u32 video_pll2_cfg2;
162 u32 dram_pll_cfg0;
163 u32 dram_pll_cfg1;
164 u32 dram_pll_cfg2;
165 u32 digprog;
166 u32 osc_misc_cfg;
167 u32 pllout_monitor_cfg;
168 u32 frac_pllout_div_cfg;
169 u32 sscg_pllout_div_cfg;
170};
171
172struct fuse_bank9_regs {
173 u32 mac_addr0;
174 u32 rsvd0[3];
175 u32 mac_addr1;
176 u32 rsvd1[11];
177};
178
179/* System Reset Controller (SRC) */
180struct src {
181 u32 scr;
182 u32 a53rcr;
183 u32 a53rcr1;
184 u32 m4rcr;
185 u32 reserved1[4];
186 u32 usbophy1_rcr;
187 u32 usbophy2_rcr;
188 u32 mipiphy_rcr;
189 u32 pciephy_rcr;
190 u32 hdmi_rcr;
191 u32 disp_rcr;
192 u32 reserved2[2];
193 u32 gpu_rcr;
194 u32 vpu_rcr;
195 u32 pcie2_rcr;
196 u32 mipiphy1_rcr;
197 u32 mipiphy2_rcr;
198 u32 reserved3;
199 u32 sbmr1;
200 u32 srsr;
201 u32 reserved4[2];
202 u32 sisr;
203 u32 simr;
204 u32 sbmr2;
205 u32 gpr1;
206 u32 gpr2;
207 u32 gpr3;
208 u32 gpr4;
209 u32 gpr5;
210 u32 gpr6;
211 u32 gpr7;
212 u32 gpr8;
213 u32 gpr9;
214 u32 gpr10;
215 u32 reserved5[985];
216 u32 ddr1_rcr;
217 u32 ddr2_rcr;
218};
219
Peng Fanb11a7342018-01-10 13:20:20 +0800220#define WDOG_WDT_MASK BIT(3)
221#define WDOG_WDZST_MASK BIT(0)
222struct wdog_regs {
223 u16 wcr; /* Control */
224 u16 wsr; /* Service */
225 u16 wrsr; /* Reset Status */
226 u16 wicr; /* Interrupt Control */
227 u16 wmcr; /* Miscellaneous Control */
228};
229
230struct bootrom_sw_info {
231 u8 reserved_1;
232 u8 boot_dev_instance;
233 u8 boot_dev_type;
234 u8 reserved_2;
235 u32 core_freq;
236 u32 axi_freq;
237 u32 ddr_freq;
238 u32 tick_freq;
239 u32 reserved_3[3];
240};
241
242#define ROM_SW_INFO_ADDR_B0 0x00000968
243#define ROM_SW_INFO_ADDR_A0 0x000009e8
244
245#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
246 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
247 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
248#endif
249#endif