Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 47065241f2723b7de7d193b4be69180d24656136 / . / arch / arm / dts / tegra20-paz00.dts
blob: cf6bd70189b867b0a7c718b4d94a4a1a410c5d62 [file] [log] [blame]
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]4
5/ {
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20";
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]13 aliases {
14 usb0 = "/usb@c5008000";
Stephen Warrend55aadc2016-09-13 10:45:43 -0600[diff] [blame]15 mmc0 = "/sdhci@c8000600";
16 mmc1 = "/sdhci@c8000000";
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]17 };
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]23 host1x@50000000 {
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]24 status = "okay";
25 dc@54200000 {
26 status = "okay";
27 rgb {
28 status = "okay";
29 nvidia,panel = <&lcd_panel>;
30 };
31 };
32 };
33
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]34 serial@70006000 {
35 clock-frequency = < 216000000 >;
36 };
37
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]38 usb@c5008000 {
39 status = "okay";
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]40 };
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]41
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]42 sdhci@c8000000 {
43 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]44 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
45 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
46 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]47 bus-width = <4>;
48 };
49
50 sdhci@c8000600 {
51 status = "okay";
52 bus-width = <8>;
Tom Warren1c77f022016-09-13 10:45:42 -0600[diff] [blame]53 non-removable;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]54 };
55
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]56 clocks {
57 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 clk32k_in: clock@0 {
62 compatible = "fixed-clock";
63 reg=<0>;
64 #clock-cells = <0>;
65 clock-frequency = <32768>;
66 };
67 };
68
Simon Glassd8af3c92016-01-30 16:38:01 -0700[diff] [blame]69 pwm: pwm@7000a000 {
70 status = "okay";
71 };
72
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]73 lcd_panel: panel {
74 /* PAZ00 has 1024x600 */
75 clock = <54030000>;
76 xres = <1024>;
77 yres = <600>;
78 right-margin = <160>;
79 left-margin = <24>;
80 hsync-len = <136>;
81 upper-margin = <3>;
82 lower-margin = <61>;
83 vsync-len = <6>;
84 hsync-active-high;
85 nvidia,bits-per-pixel = <16>;
86 nvidia,pwm = <&pwm 0 0>;
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]87 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4)
88 GPIO_ACTIVE_HIGH>;
89 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6)
90 GPIO_ACTIVE_HIGH>;
91 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
92 GPIO_ACTIVE_HIGH>;
93 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4)
94 GPIO_ACTIVE_HIGH>;
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]95 nvidia,panel-timings = <400 4 203 17 15>;
96 };
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]97};