Eric Nelson | ee61d16 | 2013-02-19 10:07:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Boundary Devices Inc. |
| 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Eric Nelson | ee61d16 | 2013-02-19 10:07:05 +0000 | [diff] [blame] | 5 | */ |
| 6 | #ifndef __ASM_ARCH_MX6_DDR_H__ |
| 7 | #define __ASM_ARCH_MX6_DDR_H__ |
| 8 | |
Tim Harvey | cce1760 | 2014-06-02 16:13:22 -0700 | [diff] [blame] | 9 | #ifndef CONFIG_SPL_BUILD |
Eric Nelson | ee61d16 | 2013-02-19 10:07:05 +0000 | [diff] [blame] | 10 | #ifdef CONFIG_MX6Q |
| 11 | #include "mx6q-ddr.h" |
| 12 | #else |
| 13 | #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) |
| 14 | #include "mx6dl-ddr.h" |
| 15 | #else |
Fabio Estevam | 712ab88 | 2014-06-24 17:40:58 -0300 | [diff] [blame] | 16 | #ifdef CONFIG_MX6SX |
| 17 | #include "mx6sx-ddr.h" |
| 18 | #else |
Eric Nelson | ee61d16 | 2013-02-19 10:07:05 +0000 | [diff] [blame] | 19 | #error "Please select cpu" |
Fabio Estevam | 712ab88 | 2014-06-24 17:40:58 -0300 | [diff] [blame] | 20 | #endif /* CONFIG_MX6SX */ |
Eric Nelson | ee61d16 | 2013-02-19 10:07:05 +0000 | [diff] [blame] | 21 | #endif /* CONFIG_MX6DL or CONFIG_MX6S */ |
| 22 | #endif /* CONFIG_MX6Q */ |
Tim Harvey | cce1760 | 2014-06-02 16:13:22 -0700 | [diff] [blame] | 23 | #else |
| 24 | |
| 25 | /* MMDC P0/P1 Registers */ |
| 26 | struct mmdc_p_regs { |
| 27 | u32 mdctl; |
| 28 | u32 mdpdc; |
| 29 | u32 mdotc; |
| 30 | u32 mdcfg0; |
| 31 | u32 mdcfg1; |
| 32 | u32 mdcfg2; |
| 33 | u32 mdmisc; |
| 34 | u32 mdscr; |
| 35 | u32 mdref; |
| 36 | u32 res1[2]; |
| 37 | u32 mdrwd; |
| 38 | u32 mdor; |
| 39 | u32 res2[3]; |
| 40 | u32 mdasp; |
| 41 | u32 res3[240]; |
| 42 | u32 mapsr; |
| 43 | u32 res4[254]; |
| 44 | u32 mpzqhwctrl; |
| 45 | u32 res5[2]; |
| 46 | u32 mpwldectrl0; |
| 47 | u32 mpwldectrl1; |
| 48 | u32 res6; |
| 49 | u32 mpodtctrl; |
| 50 | u32 mprddqby0dl; |
| 51 | u32 mprddqby1dl; |
| 52 | u32 mprddqby2dl; |
| 53 | u32 mprddqby3dl; |
| 54 | u32 res7[4]; |
| 55 | u32 mpdgctrl0; |
| 56 | u32 mpdgctrl1; |
| 57 | u32 res8; |
| 58 | u32 mprddlctl; |
| 59 | u32 res9; |
| 60 | u32 mpwrdlctl; |
| 61 | u32 res10[25]; |
| 62 | u32 mpmur0; |
| 63 | }; |
| 64 | |
| 65 | /* |
| 66 | * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL) |
| 67 | */ |
| 68 | #define MX6DQ_IOM_DDR_BASE 0x020e0500 |
| 69 | struct mx6dq_iomux_ddr_regs { |
| 70 | u32 res1[3]; |
| 71 | u32 dram_sdqs5; |
| 72 | u32 dram_dqm5; |
| 73 | u32 dram_dqm4; |
| 74 | u32 dram_sdqs4; |
| 75 | u32 dram_sdqs3; |
| 76 | u32 dram_dqm3; |
| 77 | u32 dram_sdqs2; |
| 78 | u32 dram_dqm2; |
| 79 | u32 res2[16]; |
| 80 | u32 dram_cas; |
| 81 | u32 res3[2]; |
| 82 | u32 dram_ras; |
| 83 | u32 dram_reset; |
| 84 | u32 res4[2]; |
| 85 | u32 dram_sdclk_0; |
| 86 | u32 dram_sdba2; |
| 87 | u32 dram_sdcke0; |
| 88 | u32 dram_sdclk_1; |
| 89 | u32 dram_sdcke1; |
| 90 | u32 dram_sdodt0; |
| 91 | u32 dram_sdodt1; |
| 92 | u32 res5; |
| 93 | u32 dram_sdqs0; |
| 94 | u32 dram_dqm0; |
| 95 | u32 dram_sdqs1; |
| 96 | u32 dram_dqm1; |
| 97 | u32 dram_sdqs6; |
| 98 | u32 dram_dqm6; |
| 99 | u32 dram_sdqs7; |
| 100 | u32 dram_dqm7; |
| 101 | }; |
| 102 | |
| 103 | #define MX6DQ_IOM_GRP_BASE 0x020e0700 |
| 104 | struct mx6dq_iomux_grp_regs { |
| 105 | u32 res1[18]; |
| 106 | u32 grp_b7ds; |
| 107 | u32 grp_addds; |
| 108 | u32 grp_ddrmode_ctl; |
| 109 | u32 res2; |
| 110 | u32 grp_ddrpke; |
| 111 | u32 res3[6]; |
| 112 | u32 grp_ddrmode; |
| 113 | u32 res4[3]; |
| 114 | u32 grp_b0ds; |
| 115 | u32 grp_b1ds; |
| 116 | u32 grp_ctlds; |
| 117 | u32 res5; |
| 118 | u32 grp_b2ds; |
| 119 | u32 grp_ddr_type; |
| 120 | u32 grp_b3ds; |
| 121 | u32 grp_b4ds; |
| 122 | u32 grp_b5ds; |
| 123 | u32 grp_b6ds; |
| 124 | }; |
| 125 | |
| 126 | #define MX6SDL_IOM_DDR_BASE 0x020e0400 |
| 127 | struct mx6sdl_iomux_ddr_regs { |
| 128 | u32 res1[25]; |
| 129 | u32 dram_cas; |
| 130 | u32 res2[2]; |
| 131 | u32 dram_dqm0; |
| 132 | u32 dram_dqm1; |
| 133 | u32 dram_dqm2; |
| 134 | u32 dram_dqm3; |
| 135 | u32 dram_dqm4; |
| 136 | u32 dram_dqm5; |
| 137 | u32 dram_dqm6; |
| 138 | u32 dram_dqm7; |
| 139 | u32 dram_ras; |
| 140 | u32 dram_reset; |
| 141 | u32 res3[2]; |
| 142 | u32 dram_sdba2; |
| 143 | u32 dram_sdcke0; |
| 144 | u32 dram_sdcke1; |
| 145 | u32 dram_sdclk_0; |
| 146 | u32 dram_sdclk_1; |
| 147 | u32 dram_sdodt0; |
| 148 | u32 dram_sdodt1; |
| 149 | u32 dram_sdqs0; |
| 150 | u32 dram_sdqs1; |
| 151 | u32 dram_sdqs2; |
| 152 | u32 dram_sdqs3; |
| 153 | u32 dram_sdqs4; |
| 154 | u32 dram_sdqs5; |
| 155 | u32 dram_sdqs6; |
| 156 | u32 dram_sdqs7; |
| 157 | }; |
| 158 | |
| 159 | #define MX6SDL_IOM_GRP_BASE 0x020e0700 |
| 160 | struct mx6sdl_iomux_grp_regs { |
| 161 | u32 res1[18]; |
| 162 | u32 grp_b7ds; |
| 163 | u32 grp_addds; |
| 164 | u32 grp_ddrmode_ctl; |
| 165 | u32 grp_ddrpke; |
| 166 | u32 res2[2]; |
| 167 | u32 grp_ddrmode; |
| 168 | u32 grp_b0ds; |
| 169 | u32 res3; |
| 170 | u32 grp_ctlds; |
| 171 | u32 grp_b1ds; |
| 172 | u32 grp_ddr_type; |
| 173 | u32 grp_b2ds; |
| 174 | u32 grp_b3ds; |
| 175 | u32 grp_b4ds; |
| 176 | u32 grp_b5ds; |
| 177 | u32 res4; |
| 178 | u32 grp_b6ds; |
| 179 | }; |
Tim Harvey | 8ab871b | 2014-06-02 16:13:23 -0700 | [diff] [blame] | 180 | |
| 181 | /* Device Information: Varies per DDR3 part number and speed grade */ |
| 182 | struct mx6_ddr3_cfg { |
| 183 | u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */ |
| 184 | u8 density; /* chip density (Gb) (1,2,4,8) */ |
| 185 | u8 width; /* bus width (bits) (4,8,16) */ |
| 186 | u8 banks; /* number of banks */ |
| 187 | u8 rowaddr; /* row address bits (11-16)*/ |
| 188 | u8 coladdr; /* col address bits (9-12) */ |
| 189 | u8 pagesz; /* page size (K) (1-2) */ |
| 190 | u16 trcd; /* tRCD=tRP=CL (ns*100) */ |
| 191 | u16 trcmin; /* tRC min (ns*100) */ |
| 192 | u16 trasmin; /* tRAS min (ns*100) */ |
| 193 | u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */ |
| 194 | }; |
| 195 | |
| 196 | /* System Information: Varies per board design, layout, and term choices */ |
| 197 | struct mx6_ddr_sysinfo { |
| 198 | u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */ |
| 199 | u8 cs_density; /* density per chip select (Gb) */ |
| 200 | u8 ncs; /* number chip selects used (1|2) */ |
| 201 | char cs1_mirror;/* enable address mirror (0|1) */ |
| 202 | char bi_on; /* Bank interleaving enable */ |
| 203 | u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */ |
| 204 | u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */ |
| 205 | u8 ralat; /* Read Additional Latency (0-7) */ |
| 206 | u8 walat; /* Write Additional Latency (0-3) */ |
| 207 | u8 mif3_mode; /* Command prediction working mode */ |
| 208 | u8 rst_to_cke; /* Time from SDE enable to CKE rise */ |
| 209 | u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ |
| 210 | }; |
| 211 | |
| 212 | /* |
| 213 | * Board specific calibration: |
| 214 | * This includes write leveling calibration values as well as DQS gating |
| 215 | * and read/write delays. These values are board/layout/device specific. |
| 216 | * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2 |
| 217 | * (DOC-96412) to determine these values over a range of boards and |
| 218 | * temperatures. |
| 219 | */ |
| 220 | struct mx6_mmdc_calibration { |
| 221 | /* write leveling calibration */ |
| 222 | u32 p0_mpwldectrl0; |
| 223 | u32 p0_mpwldectrl1; |
| 224 | u32 p1_mpwldectrl0; |
| 225 | u32 p1_mpwldectrl1; |
| 226 | /* read DQS gating */ |
| 227 | u32 p0_mpdgctrl0; |
| 228 | u32 p0_mpdgctrl1; |
| 229 | u32 p1_mpdgctrl0; |
| 230 | u32 p1_mpdgctrl1; |
| 231 | /* read delay */ |
| 232 | u32 p0_mprddlctl; |
| 233 | u32 p1_mprddlctl; |
| 234 | /* write delay */ |
| 235 | u32 p0_mpwrdlctl; |
| 236 | u32 p1_mpwrdlctl; |
| 237 | }; |
| 238 | |
| 239 | /* configure iomux (pinctl/padctl) */ |
| 240 | void mx6dq_dram_iocfg(unsigned width, |
| 241 | const struct mx6dq_iomux_ddr_regs *, |
| 242 | const struct mx6dq_iomux_grp_regs *); |
| 243 | void mx6sdl_dram_iocfg(unsigned width, |
| 244 | const struct mx6sdl_iomux_ddr_regs *, |
| 245 | const struct mx6sdl_iomux_grp_regs *); |
| 246 | |
| 247 | /* configure mx6 mmdc registers */ |
| 248 | void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, |
| 249 | const struct mx6_mmdc_calibration *, |
| 250 | const struct mx6_ddr3_cfg *); |
| 251 | |
Tim Harvey | cce1760 | 2014-06-02 16:13:22 -0700 | [diff] [blame] | 252 | #endif /* CONFIG_SPL_BUILD */ |
Eric Nelson | ee61d16 | 2013-02-19 10:07:05 +0000 | [diff] [blame] | 253 | |
| 254 | #define MX6_MMDC_P0_MDCTL 0x021b0000 |
| 255 | #define MX6_MMDC_P0_MDPDC 0x021b0004 |
| 256 | #define MX6_MMDC_P0_MDOTC 0x021b0008 |
| 257 | #define MX6_MMDC_P0_MDCFG0 0x021b000c |
| 258 | #define MX6_MMDC_P0_MDCFG1 0x021b0010 |
| 259 | #define MX6_MMDC_P0_MDCFG2 0x021b0014 |
| 260 | #define MX6_MMDC_P0_MDMISC 0x021b0018 |
| 261 | #define MX6_MMDC_P0_MDSCR 0x021b001c |
| 262 | #define MX6_MMDC_P0_MDREF 0x021b0020 |
| 263 | #define MX6_MMDC_P0_MDRWD 0x021b002c |
| 264 | #define MX6_MMDC_P0_MDOR 0x021b0030 |
| 265 | #define MX6_MMDC_P0_MDASP 0x021b0040 |
| 266 | #define MX6_MMDC_P0_MAPSR 0x021b0404 |
| 267 | #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800 |
| 268 | #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c |
| 269 | #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810 |
| 270 | #define MX6_MMDC_P0_MPODTCTRL 0x021b0818 |
| 271 | #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c |
| 272 | #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820 |
| 273 | #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824 |
| 274 | #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828 |
| 275 | #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c |
| 276 | #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840 |
| 277 | #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848 |
| 278 | #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850 |
| 279 | #define MX6_MMDC_P0_MPMUR0 0x021b08b8 |
| 280 | |
| 281 | #define MX6_MMDC_P1_MDCTL 0x021b4000 |
| 282 | #define MX6_MMDC_P1_MDPDC 0x021b4004 |
| 283 | #define MX6_MMDC_P1_MDOTC 0x021b4008 |
| 284 | #define MX6_MMDC_P1_MDCFG0 0x021b400c |
| 285 | #define MX6_MMDC_P1_MDCFG1 0x021b4010 |
| 286 | #define MX6_MMDC_P1_MDCFG2 0x021b4014 |
| 287 | #define MX6_MMDC_P1_MDMISC 0x021b4018 |
| 288 | #define MX6_MMDC_P1_MDSCR 0x021b401c |
| 289 | #define MX6_MMDC_P1_MDREF 0x021b4020 |
| 290 | #define MX6_MMDC_P1_MDRWD 0x021b402c |
| 291 | #define MX6_MMDC_P1_MDOR 0x021b4030 |
| 292 | #define MX6_MMDC_P1_MDASP 0x021b4040 |
| 293 | #define MX6_MMDC_P1_MAPSR 0x021b4404 |
| 294 | #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800 |
| 295 | #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c |
| 296 | #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810 |
| 297 | #define MX6_MMDC_P1_MPODTCTRL 0x021b4818 |
| 298 | #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c |
| 299 | #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820 |
| 300 | #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824 |
| 301 | #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828 |
| 302 | #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c |
| 303 | #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840 |
| 304 | #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848 |
| 305 | #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850 |
| 306 | #define MX6_MMDC_P1_MPMUR0 0x021b48b8 |
| 307 | |
| 308 | #endif /*__ASM_ARCH_MX6_DDR_H__ */ |