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git01.mediatek.com / filogic / uboot / 2ec41ef56ed21d53df02e48c82de219606b8738e / . / arch / riscv / cpu / u-boot.lds
blob: 11bc4a738b676a6fdfe868c48e87e204373e53ef [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]2/*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]5 */
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]6
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]7OUTPUT_ARCH("riscv")
8ENTRY(_start)
9
10SECTIONS
11{
12 . = ALIGN(4);
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]13 .text : {
Bin Mengbcb38432018-09-26 06:55:17 -0700[diff] [blame]14 arch/riscv/cpu/start.o (.text)
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]15 }
16
Alexander Graf94a10f22018-06-12 07:48:37 +0200[diff] [blame]17 /* This needs to come before *(.text*) */
18 .efi_runtime : {
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]19 __efi_runtime_start = .;
Alexander Graf94a10f22018-06-12 07:48:37 +0200[diff] [blame]20 *(.text.efi_runtime*)
21 *(.rodata.efi_runtime*)
22 *(.data.efi_runtime*)
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]23 __efi_runtime_stop = .;
Alexander Graf94a10f22018-06-12 07:48:37 +0200[diff] [blame]24 }
25
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]26 .text_rest : {
Alexander Graf94a10f22018-06-12 07:48:37 +0200[diff] [blame]27 *(.text*)
28 }
29
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]30 . = ALIGN(4);
31 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
32
33 . = ALIGN(4);
34 .data : {
35 __global_pointer$ = . + 0x800;
36 *(.data*)
37 }
38 . = ALIGN(4);
39
40 .got : {
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]41 __got_start = .;
42 *(.got.plt) *(.got)
43 __got_end = .;
44 }
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]45
46 . = ALIGN(4);
47
48 .u_boot_list : {
49 KEEP(*(SORT(.u_boot_list*)));
50 }
51
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]52 . = ALIGN(4);
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]53
Rick Chen9677a372018-05-28 19:06:37 +0800[diff] [blame]54 .efi_runtime_rel : {
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]55 __efi_runtime_rel_start = .;
Alexander Graf94a10f22018-06-12 07:48:37 +0200[diff] [blame]56 *(.rel*.efi_runtime)
57 *(.rel*.efi_runtime.*)
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]58 __efi_runtime_rel_stop = .;
Rick Chen9677a372018-05-28 19:06:37 +0800[diff] [blame]59 }
60
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]61 . = ALIGN(4);
Rick Chen9677a372018-05-28 19:06:37 +0800[diff] [blame]62
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]63 /DISCARD/ : { *(.rela.plt*) }
64 .rela.dyn : {
65 __rel_dyn_start = .;
66 *(.rela*)
67 __rel_dyn_end = .;
68 }
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]69
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]70 . = ALIGN(4);
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]71
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]72 .dynsym : {
73 __dyn_sym_start = .;
74 *(.dynsym)
75 __dyn_sym_end = .;
76 }
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]77
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]78 . = ALIGN(4);
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]79
80 _end = .;
81
82 .bss : {
Bin Mengc7feb192018-09-26 06:55:12 -0700[diff] [blame]83 __bss_start = .;
84 *(.bss*)
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]85 . = ALIGN(4);
86 __bss_end = .;
87 }
Rick Chene76b8042017-12-26 13:55:48 +0800[diff] [blame]88}