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git01.mediatek.com / filogic / uboot / 2e18ff2b7a2dffe034ddcf4588813dd88a8e9d8b / . / board / lubbock / lubbock.c
blob: 0daff9abf148a0e556b82e3160c111611136c79f [file] [log] [blame]
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]9 * SPDX-License-Identifier: GPL-2.0+
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]10 */
11
12#include <common.h>
Ben Warrenf0e37d12009-12-14 16:30:39 -0800[diff] [blame]13#include <netdev.h>
Marek Vasut71d058b2011-11-26 11:17:32 +0100[diff] [blame]14#include <asm/arch/pxa.h>
Marek Vasut76550692011-12-12 05:34:03 +0000[diff] [blame]15#include <asm/arch/pxa-regs.h>
Marek Vasutd2f3bbd2012-09-30 10:09:49 +0000[diff] [blame]16#include <asm/arch/regs-mmc.h>
Marek Vasut76550692011-12-12 05:34:03 +0000[diff] [blame]17#include <asm/io.h>
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]18
Wolfgang Denk6405a152006-03-31 18:32:53 +0200[diff] [blame]19DECLARE_GLOBAL_DATA_PTR;
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]20
21/*
22 * Miscelaneous platform dependent initialisations
23 */
24
25int board_init (void)
26{
Marek Vasutc5513e72010-10-20 20:55:44 +0200[diff] [blame]27 /* We have RAM, disable cache */
28 dcache_disable();
29 icache_disable();
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]30
31 /* arch number of Lubbock-Board */
wdenk767fbd42004-10-10 18:41:04 +0000[diff] [blame]32 gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]33
34 /* adress of boot parameters */
35 gd->bd->bi_boot_params = 0xa0000100;
36
Marek Vasut76550692011-12-12 05:34:03 +0000[diff] [blame]37 /* Configure GPIO6 and GPIO8 as OUT, AF1. */
38 setbits_le32(GPDR0, (1 << 6) | (1 << 8));
39 clrsetbits_le32(GAFR0_L, (3 << 12) | (3 << 16), (1 << 12) | (1 << 16));
40
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]41 return 0;
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]42}
43
Marek Vasutd2f3bbd2012-09-30 10:09:49 +0000[diff] [blame]44#ifdef CONFIG_CMD_MMC
45int board_mmc_init(bd_t *bis)
46{
47 pxa_mmc_register(0);
48 return 0;
49}
50#endif
51
wdenkda55c6e2004-01-20 23:12:12 +0000[diff] [blame]52int board_late_init(void)
wdenk7a428cc2003-06-15 22:40:42 +0000[diff] [blame]53{
wdenkda55c6e2004-01-20 23:12:12 +0000[diff] [blame]54 setenv("stdout", "serial");
55 setenv("stderr", "serial");
wdenk7a428cc2003-06-15 22:40:42 +0000[diff] [blame]56 return 0;
57}
58
Marek Vasutc5513e72010-10-20 20:55:44 +0200[diff] [blame]59int dram_init(void)
60{
Marek Vasut08341be2011-11-26 11:18:57 +0100[diff] [blame]61 pxa2xx_dram_init();
Marek Vasutc5513e72010-10-20 20:55:44 +0200[diff] [blame]62 gd->ram_size = PHYS_SDRAM_1_SIZE;
63 return 0;
64}
wdenk7a428cc2003-06-15 22:40:42 +0000[diff] [blame]65
Marek Vasutc5513e72010-10-20 20:55:44 +0200[diff] [blame]66void dram_init_banksize(void)
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]67{
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]68 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
69 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]70}
Ben Warrenf0e37d12009-12-14 16:30:39 -0800[diff] [blame]71
72#ifdef CONFIG_CMD_NET
73int board_eth_init(bd_t *bis)
74{
75 int rc = 0;
76#ifdef CONFIG_LAN91C96
77 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
78#endif
79 return rc;
80}
81#endif