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git01.mediatek.com / filogic / uboot / 2d7aa5e716dce8daa3534bb71e68b9205dd24b33 / . / arch / arm / dts / tegra20-whistler.dts
blob: 358c5824f7cc1b46b5e4991dca6c46228155f153 [file] [log] [blame]
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]4
5/ {
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]6 model = "NVIDIA Tegra20 Whistler evaluation board";
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]7 compatible = "nvidia,whistler", "nvidia,tegra20";
8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]13 aliases {
14 i2c0 = "/i2c@7000d000";
15 usb0 = "/usb@c5008000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]16 sdhci0 = "/sdhci@c8000600";
17 sdhci1 = "/sdhci@c8000400";
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]18 };
19
20 memory {
21 device_type = "memory";
22 reg = < 0x00000000 0x20000000 >;
23 };
24
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]25 serial@70006000 {
26 clock-frequency = < 216000000 >;
27 };
28
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]29 i2c@7000d000 {
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]30 status = "okay";
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]31 clock-frequency = <100000>;
32
33 pmic@3c {
34 compatible = "maxim,max8907b";
35 reg = <0x3c>;
36
37 clk_32k: clock {
38 compatible = "fixed-clock";
39 /*
40 * leave out for now due to CPP:
41 * #clock-cells = <0>;
42 */
43 clock-frequency = <32768>;
44 };
45 };
46 };
47
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]48 usb@c5008000 {
49 status = "okay";
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]50 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]51
52 sdhci@c8000400 {
53 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]54 wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]55 bus-width = <8>;
56 };
57
58 sdhci@c8000600 {
59 status = "okay";
60 bus-width = <8>;
61 };
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]62
63 clocks {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 clk32k_in: clock@0 {
69 compatible = "fixed-clock";
70 reg=<0>;
71 #clock-cells = <0>;
72 clock-frequency = <32768>;
73 };
74 };
75
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]76};