| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2011 |
| 4 | * Marvell Semiconductor <www.marvell.com> |
| 5 | * Written-by: Lei Wen <leiwen@marvell.com> |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * This file should be included in board config header file. |
| 10 | * |
| 11 | * It supports common definitions for Kirkwood platform |
| 12 | */ |
| 13 | |
| 14 | #ifndef _KW_CONFIG_H |
| 15 | #define _KW_CONFIG_H |
| 16 | |
| 17 | #if defined (CONFIG_KW88F6281) |
| 18 | #include <asm/arch/kw88f6281.h> |
| 19 | #elif defined (CONFIG_KW88F6192) |
| 20 | #include <asm/arch/kw88f6192.h> |
| 21 | #else |
| 22 | #error "SOC Name not defined" |
| 23 | #endif /* CONFIG_KW88F6281 */ |
| 24 | |
| Stefan Roese | c243784 | 2014-10-22 12:13:06 +0200 | [diff] [blame] | 25 | #include <asm/arch/soc.h> |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 26 | #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ |
| 27 | #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ |
| 28 | #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ |
| 29 | |
| 30 | /* |
| 31 | * By default kwbimage.cfg from board specific folder is used |
| 32 | * If for some board, different configuration file need to be used, |
| 33 | * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file |
| 34 | */ |
| 35 | #ifndef CONFIG_SYS_KWD_CONFIG |
| Masahiro Yamada | d6acdf2 | 2014-03-11 11:05:17 +0900 | [diff] [blame] | 36 | #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 37 | #endif /* CONFIG_SYS_KWD_CONFIG */ |
| 38 | |
| 39 | /* Kirkwood has 2k of Security SRAM, use it for SP */ |
| 40 | #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 41 | |
| Paul Kocialkowski | 2fae3e7 | 2015-04-10 23:09:51 +0200 | [diff] [blame] | 42 | #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 43 | #define MV_UART_CONSOLE_BASE KW_UART0_BASE |
| 44 | #define MV_SATA_BASE KW_SATA_BASE |
| 45 | #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET |
| 46 | #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET |
| 47 | |
| 48 | /* |
| 49 | * NAND configuration |
| 50 | */ |
| 51 | #ifdef CONFIG_CMD_NAND |
| 52 | #define CONFIG_NAND_KIRKWOOD |
| 53 | #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ |
| 54 | #define NAND_ALLOW_ERASE_ALL 1 |
| 55 | #endif |
| 56 | |
| 57 | /* |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 58 | * Ethernet Driver configuration |
| 59 | */ |
| 60 | #ifdef CONFIG_CMD_NET |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 61 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 62 | #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ |
| 63 | #endif /* CONFIG_CMD_NET */ |
| 64 | |
| 65 | /* |
| 66 | * USB/EHCI |
| 67 | */ |
| 68 | #ifdef CONFIG_CMD_USB |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 69 | #define CONFIG_EHCI_IS_TDI |
| 70 | #endif /* CONFIG_CMD_USB */ |
| 71 | |
| 72 | /* |
| 73 | * IDE Support on SATA ports |
| 74 | */ |
| Simon Glass | b569a01 | 2017-05-17 03:25:30 -0600 | [diff] [blame] | 75 | #ifdef CONFIG_IDE |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 76 | #define __io |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 77 | /* Needs byte-swapping for ATA data register */ |
| 78 | #define CONFIG_IDE_SWAP_IO |
| 79 | /* Data, registers and alternate blocks are at the same offset */ |
| 80 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) |
| 81 | #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) |
| 82 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) |
| 83 | /* Each 8-bit ATA register is aligned to a 4-bytes address */ |
| 84 | #define CONFIG_SYS_ATA_STRIDE 4 |
| 85 | /* Controller supports 48-bits LBA addressing */ |
| 86 | #define CONFIG_LBA48 |
| Simon Glass | b569a01 | 2017-05-17 03:25:30 -0600 | [diff] [blame] | 87 | /* CONFIG_IDE requires some #defines for ATA registers */ |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 88 | #define CONFIG_SYS_IDE_MAXBUS 2 |
| 89 | #define CONFIG_SYS_IDE_MAXDEVICE 2 |
| 90 | /* ATA registers base is at SATA controller base */ |
| 91 | #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE |
| Simon Glass | b569a01 | 2017-05-17 03:25:30 -0600 | [diff] [blame] | 92 | #endif /* CONFIG_IDE */ |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 93 | |
| 94 | /* |
| 95 | * I2C related stuff |
| 96 | */ |
| Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 97 | #if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C) |
| Heiko Schocher | 479a4cf | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 98 | #ifndef CONFIG_SYS_I2C_SOFT |
| Simon Glass | 0529b59 | 2021-07-10 21:14:32 -0600 | [diff] [blame] | 99 | #define CONFIG_SYS_I2C_LEGACY |
| Hans de Goede | 9830f1c | 2014-06-13 22:55:48 +0200 | [diff] [blame] | 100 | #define CONFIG_SYS_I2C_MVTWSI |
| Holger Brunck | f3f93d2 | 2011-06-16 18:11:15 +0530 | [diff] [blame] | 101 | #endif |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 102 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
| 103 | #define CONFIG_SYS_I2C_SPEED 100000 |
| 104 | #endif |
| 105 | |
| Stefan Roese | 6417489 | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 106 | /* Use common timer */ |
| 107 | #define CONFIG_SYS_TIMER_COUNTS_DOWN |
| 108 | #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) |
| 109 | #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK |
| 110 | |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 111 | #endif /* _KW_CONFIG_H */ |