| Dave Gerlach | 2c861a9 | 2021-05-11 10:22:12 -0500 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | /* |
| 3 | * Cadence DDR Driver |
| 4 | * |
| 5 | * Copyright (C) 2012-2021 Cadence Design Systems, Inc. |
| 6 | * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ |
| 7 | */ |
| 8 | |
| 9 | #ifndef LPDDR4_16BIT_IF_H |
| 10 | #define LPDDR4_16BIT_IF_H |
| 11 | |
| 12 | #include <linux/types.h> |
| 13 | |
| 14 | #define LPDDR4_INTR_MAX_CS (2U) |
| 15 | |
| 16 | #define LPDDR4_INTR_CTL_REG_COUNT (423U) |
| 17 | |
| 18 | #define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U) |
| 19 | |
| 20 | #define LPDDR4_INTR_PHY_REG_COUNT (1406U) |
| 21 | |
| 22 | typedef enum { |
| 23 | LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT = 0U, |
| 24 | LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH = 1U, |
| 25 | LPDDR4_INTR_TIMEOUT_ZQ_CALSTART = 2U, |
| 26 | LPDDR4_INTR_TIMEOUT_MRR_TEMP = 3U, |
| 27 | LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ = 4U, |
| 28 | LPDDR4_INTR_TIMEOUT_DFI_UPDATE = 5U, |
| 29 | LPDDR4_INTR_TIMEOUT_LP_WAKEUP = 6U, |
| 30 | LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX = 7U, |
| 31 | LPDDR4_INTR_ECC_ERROR = 8U, |
| 32 | LPDDR4_INTR_LP_DONE = 9U, |
| 33 | LPDDR4_INTR_LP_TIMEOUT = 10U, |
| 34 | LPDDR4_INTR_PORT_TIMEOUT = 11U, |
| 35 | LPDDR4_INTR_RFIFO_TIMEOUT = 12U, |
| 36 | LPDDR4_INTR_TRAINING_ZQ_STATUS = 13U, |
| 37 | LPDDR4_INTR_TRAINING_DQS_OSC_DONE = 14U, |
| 38 | LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE = 15U, |
| 39 | LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW = 16U, |
| 40 | LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT = 17U, |
| 41 | LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS = 18U, |
| 42 | LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS = 19U, |
| 43 | LPDDR4_INTR_USERIF_PORT_CMD_ERROR = 20U, |
| 44 | LPDDR4_INTR_USERIF_WRAP = 21U, |
| 45 | LPDDR4_INTR_USERIF_INVAL_SETTING = 22U, |
| 46 | LPDDR4_INTR_MISC_MRR_TRAFFIC = 23U, |
| 47 | LPDDR4_INTR_MISC_SW_REQ_MODE = 24U, |
| 48 | LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH = 25U, |
| 49 | LPDDR4_INTR_MISC_TEMP_ALERT = 26U, |
| 50 | LPDDR4_INTR_MISC_REFRESH_STATUS = 27U, |
| 51 | LPDDR4_INTR_BIST_DONE = 28U, |
| 52 | LPDDR4_INTR_CRC = 29U, |
| 53 | LPDDR4_INTR_DFI_UPDATE_ERROR = 30U, |
| 54 | LPDDR4_INTR_DFI_PHY_ERROR = 31U, |
| 55 | LPDDR4_INTR_DFI_BUS_ERROR = 32U, |
| 56 | LPDDR4_INTR_DFI_STATE_CHANGE = 33U, |
| 57 | LPDDR4_INTR_DFI_DLL_SYNC_DONE = 34U, |
| 58 | LPDDR4_INTR_DFI_TIMEOUT = 35U, |
| 59 | LPDDR4_INTR_DIMM = 36U, |
| 60 | LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE = 37U, |
| 61 | LPDDR4_INTR_FREQ_DFS_HW_TERMINATE = 38U, |
| 62 | LPDDR4_INTR_FREQ_DFS_HW_DONE = 39U, |
| 63 | LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE = 40U, |
| 64 | LPDDR4_INTR_FREQ_DFS_SW_TERMINATE = 41U, |
| 65 | LPDDR4_INTR_FREQ_DFS_SW_DONE = 42U, |
| 66 | LPDDR4_INTR_INIT_MEM_RESET_DONE = 43U, |
| 67 | LPDDR4_INTR_MC_INIT_DONE = 44U, |
| 68 | LPDDR4_INTR_INIT_POWER_ON_STATE = 45U, |
| 69 | LPDDR4_INTR_MRR_ERROR = 46U, |
| 70 | LPDDR4_INTR_MR_READ_DONE = 47U, |
| 71 | LPDDR4_INTR_MR_WRITE_DONE = 48U, |
| 72 | LPDDR4_INTR_PARITY_ERROR = 49U, |
| 73 | LPDDR4_INTR_LOR_BITS = 50U |
| 74 | } lpddr4_intr_ctlinterrupt; |
| 75 | |
| 76 | typedef enum { |
| 77 | LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U, |
| 78 | LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 1U, |
| 79 | LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 2U, |
| 80 | LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 3U, |
| 81 | LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 4U, |
| 82 | LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 5U, |
| 83 | LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 6U, |
| 84 | LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 7U, |
| 85 | LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 8U, |
| 86 | LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 9U, |
| 87 | LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 10U, |
| 88 | LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 11U, |
| 89 | LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 12U, |
| 90 | LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 13U, |
| 91 | LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 14U, |
| 92 | LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 15U, |
| 93 | LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 16U, |
| 94 | LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT = 17U, |
| 95 | LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT = 18U, |
| 96 | LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT = 19U, |
| 97 | LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT = 20U, |
| 98 | LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT = 21U, |
| 99 | LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT = 22U, |
| 100 | LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT = 23U, |
| 101 | LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT = 24U, |
| 102 | LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT = 25U, |
| 103 | LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT = 26U, |
| 104 | LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT = 27U, |
| 105 | LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U |
| 106 | } lpddr4_intr_phyindepinterrupt; |
| 107 | |
| 108 | #endif /* LPDDR4_16BIT_IF_H */ |