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Stelian Pop61e69d72008-05-08 20:52:22 +02001/*
2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
3 *
4 * Copyright (C) SAN People
Reinhard Meyer87b561b2010-11-19 10:04:37 +01005 * (C) Copyright 2010
6 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
Stelian Pop61e69d72008-05-08 20:52:22 +02007 *
Reinhard Meyer87b561b2010-11-19 10:04:37 +01008 * Definitions for the SoCs:
9 * AT91SAM9261, AT91SAM9G10
10 *
11 * Note that those SoCs are mostly software and pin compatible,
12 * therefore this file applies to all of them. Differences between
13 * those SoCs are concentrated at the end of this file.
Stelian Pop61e69d72008-05-08 20:52:22 +020014 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 */
20
21#ifndef AT91SAM9261_H
22#define AT91SAM9261_H
23
24/*
Reinhard Meyer87b561b2010-11-19 10:04:37 +010025 * defines to be used in other places
Stelian Pop61e69d72008-05-08 20:52:22 +020026 */
Reinhard Meyer87b561b2010-11-19 10:04:37 +010027#define CONFIG_ARM926EJS /* ARM926EJS Core */
28#define CONFIG_AT91FAMILY /* it's a member of AT91 */
Stelian Pop61e69d72008-05-08 20:52:22 +020029
Reinhard Meyer87b561b2010-11-19 10:04:37 +010030/*
31 * Peripheral identifiers/interrupts.
32 */
33#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
34#define ATMEL_ID_SYS 1 /* System Peripherals */
35#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
36#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
37#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */
38/* Reserved: 5 */
39#define ATMEL_ID_USART0 6 /* USART 0 */
40#define ATMEL_ID_USART1 7 /* USART 1 */
41#define ATMEL_ID_USART2 8 /* USART 2 */
42#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */
43#define ATMEL_ID_UDP 10 /* USB Device Port */
44#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
45#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
46#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */
47#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
48#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
49#define ATMEL_ID_SSC2 16 /* Serial Synchronous Controller 2 */
50#define ATMEL_ID_TC0 17 /* Timer Counter 0 */
51#define ATMEL_ID_TC1 18 /* Timer Counter 1 */
52#define ATMEL_ID_TC2 19 /* Timer Counter 2 */
53#define ATMEL_ID_UHP 20 /* USB Host port */
54#define ATMEL_ID_LCDC 21 /* LDC Controller */
55/* Reserved: 22-28 */
56#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
57#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
58#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
Jens Scharsig698ad062010-02-03 22:46:01 +010059
Reinhard Meyer87b561b2010-11-19 10:04:37 +010060/*
61 * User Peripherals physical base addresses.
62 */
63#define ATMEL_BASE_TCB0 0xfffa0000
64#define ATMEL_BASE_TC0 0xfffa0000
65#define ATMEL_BASE_TC1 0xfffa0040
66#define ATMEL_BASE_TC2 0xfffa0080
67#define ATMEL_BASE_UDP0 0xfffa4000
68#define ATMEL_BASE_MCI 0xfffa8000
69#define ATMEL_BASE_TWI0 0xfffac000
70#define ATMEL_BASE_USART0 0xfffb0000
71#define ATMEL_BASE_USART1 0xfffb4000
72#define ATMEL_BASE_USART2 0xfffb8000
73#define ATMEL_BASE_SSC0 0xfffbc000
74#define ATMEL_BASE_SSC1 0xfffc0000
75#define ATMEL_BASE_SSC2 0xfffc4000
76#define ATMEL_BASE_SPI0 0xfffc8000
77#define ATMEL_BASE_SPI1 0xfffcc000
78/* Reserved: 0xfffc4000 - 0xffffe9ff */
Stelian Pop61e69d72008-05-08 20:52:22 +020079
80/*
Reinhard Meyer87b561b2010-11-19 10:04:37 +010081 * System Peripherals physical base addresses.
Stelian Pop61e69d72008-05-08 20:52:22 +020082 */
Reinhard Meyer87b561b2010-11-19 10:04:37 +010083#define ATMEL_BASE_SYS 0xffffea00
84#define ATMEL_BASE_SDRAMC 0xffffea00
85#define ATMEL_BASE_SMC 0xffffec00
86#define ATMEL_BASE_MATRIX 0xffffee00
87#define ATMEL_BASE_AIC 0xfffff000
88#define ATMEL_BASE_DBGU 0xfffff200
89#define ATMEL_BASE_PIOA 0xfffff400
90#define ATMEL_BASE_PIOB 0xfffff600
91#define ATMEL_BASE_PIOC 0xfffff800
92#define ATMEL_BASE_PMC 0xfffffc00
93#define ATMEL_BASE_RSTC 0xfffffd00
94#define ATMEL_BASE_SHDWN 0xfffffd10
95#define ATMEL_BASE_RTT 0xfffffd20
96#define ATMEL_BASE_PIT 0xfffffd30
97#define ATMEL_BASE_WDT 0xfffffd40
98#define ATMEL_BASE_GPBR 0xfffffd50
Stelian Pop61e69d72008-05-08 20:52:22 +020099
Stelian Pop61e69d72008-05-08 20:52:22 +0200100/*
Reinhard Meyer87b561b2010-11-19 10:04:37 +0100101 * Internal Memory common on all these SoCs
Stelian Pop61e69d72008-05-08 20:52:22 +0200102 */
Reinhard Meyer87b561b2010-11-19 10:04:37 +0100103#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
104#define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */
Stelian Pop61e69d72008-05-08 20:52:22 +0200105
Reinhard Meyer87b561b2010-11-19 10:04:37 +0100106#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
Asen Dimov2be3b312011-07-26 01:23:39 +0000107#define ATMEL_SIZE_ROM 0x00008000 /* Internal ROM size (32Kb) */
Stelian Pop61e69d72008-05-08 20:52:22 +0200108
Reinhard Meyer87b561b2010-11-19 10:04:37 +0100109#define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */
110#define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */
Stelian Pop61e69d72008-05-08 20:52:22 +0200111
112/*
Reinhard Meyer87b561b2010-11-19 10:04:37 +0100113 * External memory
Stelian Pop61e69d72008-05-08 20:52:22 +0200114 */
Reinhard Meyer87b561b2010-11-19 10:04:37 +0100115#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
116#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
117#define ATMEL_BASE_CS2 0x30000000
118#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
119#define ATMEL_BASE_CS4 0x50000000
120#define ATMEL_BASE_CS5 0x60000000
121#define ATMEL_BASE_CS6 0x70000000
122#define ATMEL_BASE_CS7 0x80000000
Stelian Pop61e69d72008-05-08 20:52:22 +0200123
Reinhard Meyer87b561b2010-11-19 10:04:37 +0100124/*
125 * Other misc defines
126 */
127#define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */
Asen Dimov2be3b312011-07-26 01:23:39 +0000128#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
Eric Benard470a57b2011-06-06 22:48:27 +0000129#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
Stelian Pop61e69d72008-05-08 20:52:22 +0200130
Jean-Christophe PLAGNIOL-VILLARDb21aa662009-05-31 12:44:46 +0200131/*
Reinhard Meyer87b561b2010-11-19 10:04:37 +0100132 * SoC specific defines
Jean-Christophe PLAGNIOL-VILLARDb21aa662009-05-31 12:44:46 +0200133 */
Reinhard Meyer87b561b2010-11-19 10:04:37 +0100134#if defined(CONFIG_AT91SAM9261)
135# define ATMEL_CPU_NAME "AT91SAM9261"
136#elif defined(CONFIG_AT91SAM9G10)
137# define ATMEL_CPU_NAME "AT91SAM9G10"
138#endif
Stelian Pop61e69d72008-05-08 20:52:22 +0200139
140#endif