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developeraae00282018-11-15 10:07:51 +08001/*
2 * Copyright (C) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9#include "mt7623.dtsi"
10
11/ {
12 model = "Bananapi BPI-R2";
13 compatible = "bananapi,bpi-r2", "mediatek,mt7623";
14
15 chosen {
16 stdout-path = &uart2;
17 tick-timer = &timer0;
18 };
19
20 reg_1p8v: regulator-1p8v {
21 compatible = "regulator-fixed";
22 regulator-name = "fixed-1.8V";
23 regulator-min-microvolt = <1800000>;
24 regulator-max-microvolt = <1800000>;
25 regulator-boot-on;
26 regulator-always-on;
27 };
28
29 reg_3p3v: regulator-3p3v {
30 compatible = "regulator-fixed";
31 regulator-name = "fixed-3.3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 regulator-boot-on;
35 regulator-always-on;
36 };
37
38 reg_5v: regulator-5v {
39 compatible = "regulator-fixed";
40 regulator-name = "fixed-5V";
41 regulator-min-microvolt = <5000000>;
42 regulator-max-microvolt = <5000000>;
43 regulator-boot-on;
44 regulator-always-on;
45 };
46
47 leds {
48 compatible = "gpio-leds";
49
50 blue {
51 label = "bpi-r2:pio:blue";
52 gpios = <&gpio 241 GPIO_ACTIVE_HIGH>;
53 default-state = "off";
54 };
55
56 green {
57 label = "bpi-r2:pio:green";
58 gpios = <&gpio 240 GPIO_ACTIVE_HIGH>;
59 default-state = "off";
60 };
61
62 red {
63 label = "bpi-r2:pio:red";
64 gpios = <&gpio 239 GPIO_ACTIVE_HIGH>;
65 default-state = "off";
66 };
67 };
68};
69
developera9c87ba2018-12-20 16:12:54 +080070&eth {
71 status = "okay";
72 mediatek,gmac-id = <0>;
73 phy-mode = "rgmii";
74 mediatek,switch = "mt7530";
75 reset-gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
76
77 fixed-link {
78 speed = <1000>;
79 full-duplex;
80 };
81};
82
developeraae00282018-11-15 10:07:51 +080083&mmc0 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&mmc0_pins_default>;
86 status = "okay";
87 bus-width = <8>;
88 max-frequency = <50000000>;
89 cap-mmc-highspeed;
90 vmmc-supply = <&reg_3p3v>;
91 vqmmc-supply = <&reg_1p8v>;
92 non-removable;
93};
94
95&mmc1 {
96 pinctrl-names = "default";
97 pinctrl-0 = <&mmc1_pins_default>;
98 status = "okay";
99 bus-width = <4>;
100 max-frequency = <50000000>;
101 cap-sd-highspeed;
102 cd-gpios = <&gpio 261 GPIO_ACTIVE_LOW>;
103 vmmc-supply = <&reg_3p3v>;
104 vqmmc-supply = <&reg_3p3v>;
105};
106
107&pinctrl {
108 ephy_default: ephy_default {
109 mux {
110 function = "eth";
111 groups = "mdc_mdio", "ephy";
112 };
113
114 conf {
115 pins = "G2_TXEN", "G2_TXD0", "G2_TXD1", "G2_TXD2",
116 "G2_TXD3", "G2_TXC", "G2_RXC", "G2_RXD0",
117 "G2_RXD1", "G2_RXD2", "G2_RXD3", "G2_RXDV",
118 "MDC", "MDIO";
119 drive-strength = <12>;
120 mediatek,tdsel = <5>;
121 };
122 };
123
124 mmc0_pins_default: mmc0default {
125 mux {
126 function = "msdc";
127 groups = "msdc0";
128 };
129
130 conf-cmd-data {
131 pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
132 "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
133 "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
134 input-enable;
135 bias-pull-up;
136 };
137
138 conf-clk {
139 pins = "MSDC0_CLK";
140 bias-pull-down;
141 };
142
143 conf-rst {
144 pins = "MSDC0_RSTB";
145 bias-pull-up;
146 };
147 };
148
149 mmc1_pins_default: mmc1default {
150 mux {
151 function = "msdc";
152 groups = "msdc1", "msdc1_wp_0";
153 };
154
155 conf-cmd-data {
156 pins = "MSDC1_DAT0", "MSDC1_DAT1", "MSDC1_DAT2",
157 "MSDC1_DAT3", "MSDC1_DAT3", "MSDC1_CMD";
158 input-enable;
159 drive-strength = <4>;
160 bias-pull-up;
161 };
162
163 conf-clk {
164 pins = "MSDC1_CLK";
165 drive-strength = <4>;
166 };
167
168 conf-wp {
169 pins = "EINT7";
170 input-enable;
171 bias-pull-up;
172 };
173 };
174
developer9a80f0e2019-08-22 12:26:51 +0200175 pcie_default: pcie-default {
176 mux {
177 function = "pcie";
178 groups = "pcie0_0_perst", "pcie1_0_perst";
179 };
180 };
181
developeraae00282018-11-15 10:07:51 +0800182 uart0_pins_a: uart0-default {
183 mux {
184 function = "uart";
185 groups = "uart0_0_txd_rxd";
186 };
187 };
188
189 uart1_pins_a: uart1-default {
190 mux {
191 function = "uart";
192 groups = "uart1_0_txd_rxd";
193 };
194 };
195
196 uart2_pins_a: uart2-default {
197 mux {
198 function = "uart";
199 groups = "uart2_0_txd_rxd";
200 };
201 };
202
203 uart2_pins_b: uart2-alt {
204 mux {
205 function = "uart";
206 groups = "uart2_1_txd_rxd";
207 };
208 };
209};
210
developer9a80f0e2019-08-22 12:26:51 +0200211&pcie {
212 pinctrl-names = "default";
213 pinctrl-0 = <&pcie_default>;
214 status = "okay";
215
216 pcie@0,0 {
217 status = "okay";
218 };
219
220 pcie@1,0 {
221 status = "okay";
222 };
223};
224
225&pcie0_phy {
226 status = "okay";
227};
228
229&pcie1_phy {
230 status = "okay";
231};
232
developeraae00282018-11-15 10:07:51 +0800233&uart0 {
234 pinctrl-names = "default";
235 pinctrl-0 = <&uart0_pins_a>;
236 status = "okay";
237};
238
239&uart1 {
240 pinctrl-names = "default";
241 pinctrl-0 = <&uart1_pins_a>;
242 status = "okay";
243};
244
245&uart2 {
246 pinctrl-names = "default";
247 pinctrl-0 = <&uart2_pins_a>;
248 status = "okay";
249};