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git01.mediatek.com / filogic / uboot / 21136db879f60bdf6501613b8c3eeb20d5f11c51 / . / include / configs / FADS823.h
blob: acb2eed2a8a2ca2fd3b2c3d677a9b8c5b17ff6be [file] [log] [blame]
wdenk5b1d7132002-11-03 00:07:02 +0000[diff] [blame]1 /*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
6 *
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
8 */
9
10/*
11 * 1999-nov-26: The FADS is using the following physical memorymap:
12 *
13 * ff020000 -> ff02ffff : pcmcia io remapping
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia
17 * fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot
18 * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
19*/
20
21#define CFG_PCMCIA_IO_ADDR 0xff020000
22#define CFG_PCMCIA_IO_SIZE 0x10000
23#define CFG_PCMCIA_MEM_ADDR 0xe0000000
24#define CFG_PCMCIA_MEM_SIZE 0x10000
25#define CFG_IMMR 0xFF000000
26#define CFG_SDRAM_BASE 0x00000000
27#define CFG_FLASH_BASE 0x02800000
28#define BCSR_ADDR ((uint) 0xff010000)
29#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
30
31/* ------------------------------------------------------------------------- */
32
33/*
34 * board/config.h - configuration options, board specific
35 */
36
37#ifndef __CONFIG_H
38#define __CONFIG_H
39
40#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
41#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
42
43#define CONFIG_VIDEO 1 /* To enable video controller support */
44#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
45#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
46#define CFG_I2C_SLAVE 0x7F
47
48/*Now included by CFG_CMD_PCMCIA */
49/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
50
51/* Video related */
52
53#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
54#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
55#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
56#define CONFIG_VIDEO_SIZE (2*1024*1024)
57/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
58
59/* Wireless 56Khz 4PPM keyboard on SMCx */
60
wdenk4e112c12003-06-03 23:54:09 +0000[diff] [blame]61/*#define CONFIG_KEYBOARD 1 */
wdenk5b1d7132002-11-03 00:07:02 +0000[diff] [blame]62#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
63
64/*
65 * High Level Configuration Options
66 * (easy to change)
67 */
68#include <mpc8xx_irq.h>
69
70#define CONFIG_MPC823 1
71#define CONFIG_MPC823FADS 1
72#define CONFIG_FADS 1
73
74#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
75#undef CONFIG_8xx_CONS_SMC2
76#undef CONFIG_8xx_CONS_NONE
77#define CONFIG_BAUDRATE 115200
78
79/* Set the CPU speed to 50Mhz on the FADS */
80
81#if 0
82#define MPC8XX_FACT 10 /* Multiply by 10 */
83#define MPC8XX_XIN 5000000 /* 5 MHz in */
84#else
85#define MPC8XX_FACT 10 /* Multiply by 10 */
86#define MPC8XX_XIN 5000000 /* 5 MHz in */
87#define CFG_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */
88#endif
89#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
90
91#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
92
93#if 1
94#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
95#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
96#define CONFIG_BOOTARGS ""
97#define CONFIG_BOOTCOMMAND \
98"bootp ;" \
99"setenv bootargs console=tty0 console=ttyS0 " \
100"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " \
101"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off ;" \
102"bootm"
103#else
104#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
105#endif
106
107#undef CONFIG_WATCHDOG /* watchdog disabled */
108
109#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
110
111/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
112#include <cmd_confdefs.h>
113
114/*
115 * Miscellaneous configurable options
116 */
117#define CFG_LONGHELP /* undef to save memory */
118#define CFG_PROMPT ":>" /* Monitor Command Prompt */
119#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
120#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
121#else
122#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
123#endif
124#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
125#define CFG_MAXARGS 16 /* max number of command args */
126#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
127
128#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
129#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */
130
131#define CFG_LOAD_ADDR 0x00100000 /* default load address */
132
133#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
134
135#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
136
137/*
138 * Low Level Configuration Settings
139 * (address mappings, register initial values, etc.)
140 * You should know what you are doing if you make changes here.
141 */
142/*-----------------------------------------------------------------------
143 * Internal Memory Mapped Register
144 */
145#define CFG_IMMR_SIZE ((uint)(64 * 1024))
146
147/*-----------------------------------------------------------------------
148 * Definitions for initial stack pointer and data area (in DPRAM)
149 */
150#define CFG_INIT_RAM_ADDR CFG_IMMR
151#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
152#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
153#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
154#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
155
156/*-----------------------------------------------------------------------
157 * Start addresses for the final memory configuration
158 * (Set up by the startup code)
159 * Please note that CFG_SDRAM_BASE _must_ start at 0
160 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
161 */
162#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
163#if 0
164#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
165#else
166#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
167#endif
168#define CFG_MONITOR_BASE CFG_FLASH_BASE
169#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
170
171/*
172 * For booting Linux, the board info and command line data
173 * have to be in the first 8 MB of memory, since this is
174 * the maximum mapped by the Linux kernel during initialization.
175 */
176#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
177/*-----------------------------------------------------------------------
178 * FLASH organization
179 */
180#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
181#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
182
183#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
184#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
185
186#define CFG_ENV_IS_IN_FLASH 1
187#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
188#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
189
190/*-----------------------------------------------------------------------
191 * Cache Configuration
192 */
193#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
194#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
195#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
196#endif
197
198/*-----------------------------------------------------------------------
199 * SYPCR - System Protection Control 11-9
200 * SYPCR can only be written once after reset!
201 *-----------------------------------------------------------------------
202 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
203 */
204#if defined(CONFIG_WATCHDOG)
205#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
206 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
207#else
208#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
209#endif
210
211/*-----------------------------------------------------------------------
212 * SIUMCR - SIU Module Configuration 11-6
213 *-----------------------------------------------------------------------
214 * PCMCIA config., multi-function pin tri-state
215 */
216#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
217
218/*-----------------------------------------------------------------------
219 * TBSCR - Time Base Status and Control 11-26
220 *-----------------------------------------------------------------------
221 * Clear Reference Interrupt Status, Timebase freezing enabled
222 */
223#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
224
225/*-----------------------------------------------------------------------
226 * PISCR - Periodic Interrupt Status and Control 11-31
227 *-----------------------------------------------------------------------
228 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
229 */
230#define CFG_PISCR (PISCR_PS | PISCR_PITF)
231
232/*-----------------------------------------------------------------------
233 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
234 *-----------------------------------------------------------------------
235 * Reset PLL lock status sticky bit, timer expired status bit and timer *
236 * interrupt status bit - leave PLL multiplication factor unchanged !
237 */
238#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
239
240/*-----------------------------------------------------------------------
241 * SCCR - System Clock and reset Control Register 15-27
242 *-----------------------------------------------------------------------
243 * Set clock output, timebase and RTC source and divider,
244 * power management and some other internal clocks
245 */
246#define SCCR_MASK SCCR_EBDF11
247#define CFG_SCCR (SCCR_TBS | \
248 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
249 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
250 SCCR_DFALCD00)
251
252 /*-----------------------------------------------------------------------
253 *
254 *-----------------------------------------------------------------------
255 *
256 */
257#define CFG_DER 0
258
259/* Because of the way the 860 starts up and assigns CS0 the
260* entire address space, we have to set the memory controller
261* differently. Normally, you write the option register
262* first, and then enable the chip select by writing the
263* base register. For CS0, you must write the base register
264* first, followed by the option register.
265*/
266
267/*
268 * Init Memory Controller:
269 *
270 * BR0/1 and OR0/1 (FLASH)
271 */
272/* the other CS:s are determined by looking at parameters in BCSRx */
273
274#define BCSR_SIZE ((uint)(64 * 1024))
275
276#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
277
278#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
279#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
280
281/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
282#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
283
284#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
285#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
286#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
287
288/* BCSRx - Board Control and Status Registers */
289#define CFG_OR1_REMAP CFG_OR0_REMAP
290#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
291#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
292
293
294/*
295 * Memory Periodic Timer Prescaler
296 */
297
298/* periodic timer for refresh */
299#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
300
301/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
302#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
303#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
304
305/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
306#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
307#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
308
309/*
310 * MAMR settings for SDRAM
311 */
312
313/* 8 column SDRAM */
314#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
315 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
316 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
317/* 9 column SDRAM */
318#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
319 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
320 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
321
322#define CFG_MAMR 0x13a01114
323/*
324 * Internal Definitions
325 *
326 * Boot Flags
327 */
328#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
329#define BOOTFLAG_WARM 0x02 /* Software reboot */
330
331/* values according to the manual */
332
333#define BCSR0 ((uint) (BCSR_ADDR + 00))
334#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
335#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
336#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
337#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
338
339/* FADS bitvalues by Helmut Buchsbaum
340 * see MPC8xxADS User's Manual for a proper description
341 * of the following structures
342 */
343
344#define BCSR0_ERB ((uint)0x80000000)
345#define BCSR0_IP ((uint)0x40000000)
346#define BCSR0_BDIS ((uint)0x10000000)
347#define BCSR0_BPS_MASK ((uint)0x0C000000)
348#define BCSR0_ISB_MASK ((uint)0x01800000)
349#define BCSR0_DBGC_MASK ((uint)0x00600000)
350#define BCSR0_DBPC_MASK ((uint)0x00180000)
351#define BCSR0_EBDF_MASK ((uint)0x00060000)
352
353#define BCSR1_FLASH_EN ((uint)0x80000000)
354#define BCSR1_DRAM_EN ((uint)0x40000000)
355#define BCSR1_ETHEN ((uint)0x20000000)
356#define BCSR1_IRDEN ((uint)0x10000000)
357#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
358#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
359#define BCSR1_BCSR_EN ((uint)0x02000000)
360#define BCSR1_RS232EN_1 ((uint)0x01000000)
361#define BCSR1_PCCEN ((uint)0x00800000)
362#define BCSR1_PCCVCC0 ((uint)0x00400000)
363#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
364#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
365#define BCSR1_RS232EN_2 ((uint)0x00040000)
366#define BCSR1_SDRAM_EN ((uint)0x00020000)
367#define BCSR1_PCCVCC1 ((uint)0x00010000)
368
369#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
370#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
371#define BCSR2_DRAM_PD_SHIFT (23)
372#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
373#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
374
375#define BCSR3_DBID_MASK ((ushort)0x3800)
376#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
377#define BCSR3_BREVNR0 ((ushort)0x0080)
378#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
379#define BCSR3_BREVN1 ((ushort)0x0008)
380#define BCSR3_BREVN2_MASK ((ushort)0x0003)
381
382#define BCSR4_ETHLOOP ((uint)0x80000000)
383#define BCSR4_TFPLDL ((uint)0x40000000)
384#define BCSR4_TPSQEL ((uint)0x20000000)
385#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
386#ifdef CONFIG_MPC823
387#define BCSR4_USB_EN ((uint)0x08000000)
388#endif /* CONFIG_MPC823 */
389#ifdef CONFIG_MPC860SAR
390#define BCSR4_UTOPIA_EN ((uint)0x08000000)
391#endif /* CONFIG_MPC860SAR */
392#ifdef CONFIG_MPC860T
393#define BCSR4_FETH_EN ((uint)0x08000000)
394#endif /* CONFIG_MPC860T */
395#ifdef CONFIG_MPC823
396#define BCSR4_USB_SPEED ((uint)0x04000000)
397#endif /* CONFIG_MPC823 */
398#ifdef CONFIG_MPC860T
399#define BCSR4_FETHCFG0 ((uint)0x04000000)
400#endif /* CONFIG_MPC860T */
401#ifdef CONFIG_MPC823
402#define BCSR4_VCCO ((uint)0x02000000)
403#endif /* CONFIG_MPC823 */
404#ifdef CONFIG_MPC860T
405#define BCSR4_FETHFDE ((uint)0x02000000)
406#endif /* CONFIG_MPC860T */
407#ifdef CONFIG_MPC823
408#define BCSR4_VIDEO_ON ((uint)0x00800000)
409#endif /* CONFIG_MPC823 */
410#ifdef CONFIG_MPC823
411#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
412#endif /* CONFIG_MPC823 */
413#ifdef CONFIG_MPC860T
414#define BCSR4_FETHCFG1 ((uint)0x00400000)
415#endif /* CONFIG_MPC860T */
416#ifdef CONFIG_MPC823
417#define BCSR4_VIDEO_RST ((uint)0x00200000)
418#endif /* CONFIG_MPC823 */
419#ifdef CONFIG_MPC860T
420#define BCSR4_FETHRST ((uint)0x00200000)
421#endif /* CONFIG_MPC860T */
422#ifdef CONFIG_MPC823
423#define BCSR4_MODEM_EN ((uint)0x00100000)
424#endif /* CONFIG_MPC823 */
425#ifdef CONFIG_MPC823
426#define BCSR4_DATA_VOICE ((uint)0x00080000)
427#endif /* CONFIG_MPC823 */
428#ifdef CONFIG_MPC850
429#define BCSR4_DATA_VOICE ((uint)0x00080000)
430#endif /* CONFIG_MPC850 */
431
432#define CONFIG_DRAM_50MHZ 1
433#define CONFIG_SDRAM_50MHZ
434
435#ifdef CONFIG_MPC860T
436
437/* Interrupt level assignments.
438*/
439#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
440
441#endif /* CONFIG_MPC860T */
442
443/* We don't use the 8259.
444*/
445#define NR_8259_INTS 0
446
447/* Machine type
448*/
449#define _MACH_8xx (_MACH_fads)
450
451/*
452 * MPC8xx CPM Options
453 */
454#define CONFIG_SCC_ENET 1
455#define CONFIG_SCC2_ENET 1
456#undef CONFIG_FEC_ENET
457#undef CONFIG_CPM_IIC
458#undef CONFIG_UCODE_PATCH
459
460#define CONFIG_DISK_SPINUP_TIME 1000000
461
462/* PCMCIA configuration */
463
464#define PCMCIA_MAX_SLOTS 1
465
466#ifdef CONFIG_MPC860
467#define PCMCIA_SLOT_A 1
468#endif
469
470#endif /* __CONFIG_H */