blob: c6b23e4c6908cc7043f271960fd1702fe8ec3fce [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shengzhou Liud11b3cb2014-04-18 16:43:39 +08002/* Copyright 2013 Freescale Semiconductor, Inc.
Shengzhou Liud11b3cb2014-04-18 16:43:39 +08003 */
4
5#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07006#include <clock_legacy.h>
Simon Glassa73bda42015-11-08 23:47:45 -07007#include <console.h>
Simon Glass9d1f6192019-08-02 09:44:25 -06008#include <env_internal.h>
Simon Glass284f71b2019-12-28 10:44:45 -07009#include <init.h>
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080010#include <malloc.h>
11#include <ns16550.h>
12#include <nand.h>
13#include <i2c.h>
14#include <mmc.h>
15#include <fsl_esdhc.h>
16#include <spi_flash.h>
17#include "../common/qixis.h"
18#include "t208xqds_qixis.h"
Simon Glassdd8e2242016-09-24 18:20:10 -060019#include "../common/spl.h"
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080020
21DECLARE_GLOBAL_DATA_PTR;
22
23phys_size_t get_effective_memsize(void)
24{
25 return CONFIG_SYS_L3_SIZE;
26}
27
28unsigned long get_board_sys_clk(void)
29{
30 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
31
32 switch (sysclk_conf & 0x0F) {
33 case QIXIS_SYSCLK_83:
34 return 83333333;
35 case QIXIS_SYSCLK_100:
36 return 100000000;
37 case QIXIS_SYSCLK_125:
38 return 125000000;
39 case QIXIS_SYSCLK_133:
40 return 133333333;
41 case QIXIS_SYSCLK_150:
42 return 150000000;
43 case QIXIS_SYSCLK_160:
44 return 160000000;
45 case QIXIS_SYSCLK_166:
46 return 166666666;
47 }
48 return 66666666;
49}
50
51unsigned long get_board_ddr_clk(void)
52{
53 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
54
55 switch ((ddrclk_conf & 0x30) >> 4) {
56 case QIXIS_DDRCLK_100:
57 return 100000000;
58 case QIXIS_DDRCLK_125:
59 return 125000000;
60 case QIXIS_DDRCLK_133:
61 return 133333333;
62 }
63 return 66666666;
64}
65
66void board_init_f(ulong bootflag)
67{
68 u32 plat_ratio, sys_clk, ccb_clk;
69 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
70
71 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
72 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
73
74 /* Update GD pointer */
75 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
76
77 console_init_f();
78
79 /* initialize selected port with appropriate baud rate */
80 sys_clk = get_board_sys_clk();
81 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
82 ccb_clk = sys_clk * plat_ratio / 2;
83
Simon Glass119e7ef2020-12-22 19:30:18 -070084 NS16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080085 ccb_clk / 16 / CONFIG_BAUDRATE);
86
87#if defined(CONFIG_SPL_MMC_BOOT)
88 puts("\nSD boot...\n");
89#elif defined(CONFIG_SPL_SPI_BOOT)
90 puts("\nSPI boot...\n");
91#elif defined(CONFIG_SPL_NAND_BOOT)
92 puts("\nNAND boot...\n");
93#endif
94
95 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
96}
97
98void board_init_r(gd_t *gd, ulong dest_addr)
99{
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900100 struct bd_info *bd;
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800101
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900102 bd = (struct bd_info *)(gd + sizeof(gd_t));
103 memset(bd, 0, sizeof(struct bd_info));
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800104 gd->bd = bd;
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800105
Simon Glass302445a2017-01-23 13:31:22 -0700106 arch_cpu_init();
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800107 get_clocks();
108 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
109 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garg2ff056b2016-05-25 12:41:48 -0400110 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800111
112#ifdef CONFIG_SPL_NAND_BOOT
113 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -0500114 (uchar *)SPL_ENV_ADDR);
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800115#endif
116#ifdef CONFIG_SPL_MMC_BOOT
117 mmc_initialize(bd);
118 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -0500119 (uchar *)SPL_ENV_ADDR);
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800120#endif
121#ifdef CONFIG_SPL_SPI_BOOT
Simon Glassdd8e2242016-09-24 18:20:10 -0600122 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -0500123 (uchar *)SPL_ENV_ADDR);
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800124#endif
125
Tom Rini5cd7ece2019-11-18 20:02:10 -0500126 gd->env_addr = (ulong)(SPL_ENV_ADDR);
Simon Glass4bc2ad22017-08-03 12:21:56 -0600127 gd->env_valid = ENV_VALID;
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800128
129 i2c_init_all();
130
Simon Glassd35f3382017-04-06 12:47:05 -0600131 dram_init();
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800132
133#ifdef CONFIG_SPL_MMC_BOOT
134 mmc_boot();
135#elif defined(CONFIG_SPL_SPI_BOOT)
Simon Glassdd8e2242016-09-24 18:20:10 -0600136 fsl_spi_boot();
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800137#elif defined(CONFIG_SPL_NAND_BOOT)
138 nand_boot();
139#endif
140}