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git01.mediatek.com / filogic / uboot / 2b21598d13a5c3868075df318ff37ea4536baaa0 / . / board / freescale / mx31ads / lowlevel_init.S
blob: fcb5549d77414101d43a262a478ab7b6929eb700 [file] [log] [blame]
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200[diff] [blame]1/*
2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200[diff] [blame]5 */
6
Stefano Babic78129d92011-03-14 15:43:56 +0100[diff] [blame]7#include <asm/arch/imx-regs.h>
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200[diff] [blame]8
9.macro REG reg, val
10 ldr r2, =\reg
11 ldr r3, =\val
12 str r3, [r2]
13.endm
14
15.macro REG8 reg, val
16 ldr r2, =\reg
17 ldr r3, =\val
18 strb r3, [r2]
19.endm
20
21.macro DELAY loops
22 ldr r2, =\loops
231:
24 subs r2, r2, #1
25 nop
26 bcs 1b
27.endm
28
29/* RedBoot: AIPS setup - Only setup MPROTx registers.
30 * The PACR default values are good.*/
31.macro init_aips
32 /*
33 * Set all MPROTx to be non-bufferable, trusted for R/W,
34 * not forced to user-mode.
35 */
36 ldr r0, =0x43F00000
37 ldr r1, =0x77777777
38 str r1, [r0, #0x00]
39 str r1, [r0, #0x04]
40 ldr r0, =0x53F00000
41 str r1, [r0, #0x00]
42 str r1, [r0, #0x04]
43
44 /*
45 * Clear the on and off peripheral modules Supervisor Protect bit
46 * for SDMA to access them. Did not change the AIPS control registers
47 * (offset 0x20) access type
48 */
49 ldr r0, =0x43F00000
50 ldr r1, =0x0
51 str r1, [r0, #0x40]
52 str r1, [r0, #0x44]
53 str r1, [r0, #0x48]
54 str r1, [r0, #0x4C]
55 ldr r1, [r0, #0x50]
56 and r1, r1, #0x00FFFFFF
57 str r1, [r0, #0x50]
58
59 ldr r0, =0x53F00000
60 ldr r1, =0x0
61 str r1, [r0, #0x40]
62 str r1, [r0, #0x44]
63 str r1, [r0, #0x48]
64 str r1, [r0, #0x4C]
65 ldr r1, [r0, #0x50]
66 and r1, r1, #0x00FFFFFF
67 str r1, [r0, #0x50]
68.endm /* init_aips */
69
70/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
71.macro init_max
72 ldr r0, =0x43F04000
73 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
74 ldr r1, =0x00302154
75 str r1, [r0, #0x000] /* for S0 */
76 str r1, [r0, #0x100] /* for S1 */
77 str r1, [r0, #0x200] /* for S2 */
78 str r1, [r0, #0x300] /* for S3 */
79 str r1, [r0, #0x400] /* for S4 */
80 /* SGPCR - always park on last master */
81 ldr r1, =0x10
82 str r1, [r0, #0x010] /* for S0 */
83 str r1, [r0, #0x110] /* for S1 */
84 str r1, [r0, #0x210] /* for S2 */
85 str r1, [r0, #0x310] /* for S3 */
86 str r1, [r0, #0x410] /* for S4 */
87 /* MGPCR - restore default values */
88 ldr r1, =0x0
89 str r1, [r0, #0x800] /* for M0 */
90 str r1, [r0, #0x900] /* for M1 */
91 str r1, [r0, #0xA00] /* for M2 */
92 str r1, [r0, #0xB00] /* for M3 */
93 str r1, [r0, #0xC00] /* for M4 */
94 str r1, [r0, #0xD00] /* for M5 */
95.endm /* init_max */
96
97/* RedBoot: M3IF setup */
98.macro init_m3if
99 /* Configure M3IF registers */
100 ldr r1, =0xB8003000
101 /*
102 * M3IF Control Register (M3IFCTL)
103 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
104 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
105 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
106 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
107 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
108 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
109 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
110 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
111 * ------------
112 * 0x00000040
113 */
114 ldr r0, =0x00000040
115 str r0, [r1] /* M3IF control reg */
116.endm /* init_m3if */
117
118/* RedBoot: To support 133MHz DDR */
119.macro init_drive_strength
120 /*
121 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
122 * in SW_PAD_CTL registers
123 */
124
125 /* SDCLK */
126 ldr r1, =0x43FAC200
127 ldr r0, [r1, #0x6C]
128 bic r0, r0, #(1 << 12)
129 str r0, [r1, #0x6C]
130
131 /* CAS */
132 ldr r0, [r1, #0x70]
133 bic r0, r0, #(1 << 22)
134 str r0, [r1, #0x70]
135
136 /* RAS */
137 ldr r0, [r1, #0x74]
138 bic r0, r0, #(1 << 2)
139 str r0, [r1, #0x74]
140
141 /* CS2 (CSD0) */
142 ldr r0, [r1, #0x7C]
143 bic r0, r0, #(1 << 22)
144 str r0, [r1, #0x7C]
145
146 /* DQM3 */
147 ldr r0, [r1, #0x84]
148 bic r0, r0, #(1 << 22)
149 str r0, [r1, #0x84]
150
151 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
152 ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
153pad_loop:
154 ldr r0, [r1, #0x88]
155 bic r0, r0, #(1 << 22)
156 bic r0, r0, #(1 << 12)
157 bic r0, r0, #(1 << 2)
158 str r0, [r1, #0x88]
159 add r1, r1, #4
160 subs r2, r2, #0x1
161 bne pad_loop
162.endm /* init_drive_strength */
163
164/* CPLD on CS4 setup */
165.macro init_cs4
166 ldr r0, =WEIM_BASE
167 ldr r1, =0x0000D843
168 str r1, [r0, #0x40]
169 ldr r1, =0x22252521
170 str r1, [r0, #0x44]
171 ldr r1, =0x22220A00
172 str r1, [r0, #0x48]
173.endm /* init_cs4 */
174
175.globl lowlevel_init
176lowlevel_init:
177
178 /* Redboot initializes very early AIPS, what for?
179 * Then it also initializes Multi-Layer AHB Crossbar Switch,
180 * M3IF */
181 /* Also setup the Peripheral Port Remap register inside the core */
182 ldr r0, =0x40000015 /* start from AIPS 2GB region */
183 mcr p15, 0, r0, c15, c2, 4
184
185 init_aips
186
187 init_max
188
189 init_m3if
190
191 init_drive_strength
192
193 init_cs4
194
195 /* Image Processing Unit: */
196 /* Too early to switch display on? */
197 REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */
198 /* Clock Control Module: */
199 REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
200
201 DELAY 0x40000
202
203 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
204 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */
205
206 /* PBC CPLD on CS4 */
207 mov r1, #CS4_BASE
208 ldrh r1, [r1, #0x2]
209 /* Is 27MHz switch set? */
Guennadi Liakhovetski08601a62008-05-08 10:09:27 +0200[diff] [blame]210 ands r1, r1, #0x10
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200[diff] [blame]211
212 /* 532-133-66.5 */
213 ldr r0, =CCM_BASE
214 ldr r1, =0xFF871D58
215 /* PDR0 */
216 str r1, [r0, #0x4]
217 ldreq r1, MPCTL_PARAM_532
218 ldrne r1, MPCTL_PARAM_532_27
219 /* MPCTL */
220 str r1, [r0, #0x10]
221
222 /* Set UPLL=240MHz, USB=60MHz */
223 ldr r1, =0x49FCFE7F
224 /* PDR1 */
225 str r1, [r0, #0x8]
226 ldreq r1, UPCTL_PARAM_240
227 ldrne r1, UPCTL_PARAM_240_27
228 /* UPCTL */
229 str r1, [r0, #0x14]
230 /* default CLKO to 1/8 of the ARM core */
231 mov r1, #0x000002C0
232 add r1, r1, #0x00000006
233 /* COSR */
234 str r1, [r0, #0x1c]
235
Benoît Thébaudeaua83d2a92012-08-14 08:43:07 +0000[diff] [blame]236 /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
237/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200[diff] [blame]238
239 /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
240/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
241 /* Default: 1, 4, 12, 1 */
242 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
243
244 /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
245 REG 0xB8001010, 0x00000004
246 REG 0xB8001004, 0x006ac73a
247 REG 0xB8001000, 0x92100000
248 REG 0x80000f00, 0x12344321
249 REG 0xB8001000, 0xa2100000
250 REG 0x80000000, 0x12344321
251 REG 0x80000000, 0x12344321
252 REG 0xB8001000, 0xb2100000
253 REG8 0x80000033, 0xda
254 REG8 0x81000000, 0xff
255 REG 0xB8001000, 0x82226080
256 REG 0x80000000, 0xDEADBEEF
257 REG 0xB8001010, 0x0000000c
258
259 mov pc, lr
260
261MPCTL_PARAM_532:
262 .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
263MPCTL_PARAM_532_27:
264 .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
265UPCTL_PARAM_240:
266 .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
267UPCTL_PARAM_240_27:
268 .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))