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git01.mediatek.com / filogic / uboot / 2ae9f5ac536eb12209878cdd70d4eec9f34bdf7d / . / arch / arm / include / asm / arch-mx7ulp / scg.h
blob: 3b5b7f6803ce10f2e419e5612469a6ad785d59a8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Peng Fan684ccd92017-02-22 16:21:42 +0800[diff] [blame]2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
Peng Fan684ccd92017-02-22 16:21:42 +0800[diff] [blame]4 */
5
6#ifndef _ASM_ARCH_SCG_H
7#define _ASM_ARCH_SCG_H
8
Peng Fan684ccd92017-02-22 16:21:42 +0800[diff] [blame]9#ifdef CONFIG_CLK_DEBUG
10#define clk_debug(fmt, args...) printf(fmt, ##args)
11#else
12#define clk_debug(fmt, args...)
13#endif
14
15#define SCG_CCR_SCS_SHIFT (24)
16#define SCG_CCR_SCS_MASK ((0xFUL) << SCG_CCR_SCS_SHIFT)
17#define SCG_CCR_DIVCORE_SHIFT (16)
18#define SCG_CCR_DIVCORE_MASK ((0xFUL) << SCG_CCR_DIVCORE_SHIFT)
19#define SCG_CCR_DIVPLAT_SHIFT (12)
20#define SCG_CCR_DIVPLAT_MASK ((0xFUL) << SCG_CCR_DIVPLAT_SHIFT)
21#define SCG_CCR_DIVEXT_SHIFT (8)
22#define SCG_CCR_DIVEXT_MASK ((0xFUL) << SCG_CCR_DIVEXT_SHIFT)
23#define SCG_CCR_DIVBUS_SHIFT (4)
24#define SCG_CCR_DIVBUS_MASK ((0xFUL) << SCG_CCR_DIVBUS_SHIFT)
25#define SCG_CCR_DIVSLOW_SHIFT (0)
26#define SCG_CCR_DIVSLOW_MASK ((0xFUL) << SCG_CCR_DIVSLOW_SHIFT)
27
28/* SCG DDR Clock Control Register */
29#define SCG_DDRCCR_DDRCS_SHIFT (24)
30#define SCG_DDRCCR_DDRCS_MASK ((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT)
31
32#define SCG_DDRCCR_DDRDIV_SHIFT (0)
33#define SCG_DDRCCR_DDRDIV_MASK ((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT)
34
35/* SCG NIC Clock Control Register */
36#define SCG_NICCCR_NICCS_SHIFT (28)
37#define SCG_NICCCR_NICCS_MASK ((0x1UL) << SCG_NICCCR_NICCS_SHIFT)
38
39#define SCG_NICCCR_NIC0_DIV_SHIFT (24)
40#define SCG_NICCCR_NIC0_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT)
41
42#define SCG_NICCCR_GPU_DIV_SHIFT (20)
43#define SCG_NICCCR_GPU_DIV_MASK ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT)
44
45#define SCG_NICCCR_NIC1_DIV_SHIFT (16)
46#define SCG_NICCCR_NIC1_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT)
47
48#define SCG_NICCCR_NIC1_DIVEXT_SHIFT (8)
49#define SCG_NICCCR_NIC1_DIVEXT_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT)
50
51#define SCG_NICCCR_NIC1_DIVBUS_SHIFT (4)
52#define SCG_NICCCR_NIC1_DIVBUS_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
53
54/* SCG NIC clock status register */
55#define SCG_NICCSR_NICCS_SHIFT (28)
56#define SCG_NICCSR_NICCS_MASK ((0x1UL) << SCG_NICCSR_NICCS_SHIFT)
57
58#define SCG_NICCSR_NIC0DIV_SHIFT (24)
59#define SCG_NICCSR_NIC0DIV_MASK ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT)
60#define SCG_NICCSR_GPUDIV_SHIFT (20)
61#define SCG_NICCSR_GPUDIV_MASK ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT)
62#define SCG_NICCSR_NIC1DIV_SHIFT (16)
63#define SCG_NICCSR_NIC1DIV_MASK ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT)
64#define SCG_NICCSR_NIC1EXTDIV_SHIFT (8)
65#define SCG_NICCSR_NIC1EXTDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT)
66#define SCG_NICCSR_NIC1BUSDIV_SHIFT (4)
67#define SCG_NICCSR_NIC1BUSDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT)
68
69/* SCG Slow IRC Control Status Register */
70#define SCG_SIRC_CSR_SIRCVLD_SHIFT (24)
71#define SCG_SIRC_CSR_SIRCVLD_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT)
72
73#define SCG_SIRC_CSR_SIRCEN_SHIFT (0)
74#define SCG_SIRC_CSR_SIRCEN_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT)
75
76/* SCG Slow IRC Configuration Register */
77#define SCG_SIRCCFG_RANGE_SHIFT (0)
78#define SCG_SIRCCFG_RANGE_MASK ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
79#define SCG_SIRCCFG_RANGE_4M ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT)
80#define SCG_SIRCCFG_RANGE_16M ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
81
82/* SCG Slow IRC Divide Register */
83#define SCG_SIRCDIV_DIV3_SHIFT (16)
84#define SCG_SIRCDIV_DIV3_MASK ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT)
85
86#define SCG_SIRCDIV_DIV2_SHIFT (8)
87#define SCG_SIRCDIV_DIV2_MASK ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT)
88
89#define SCG_SIRCDIV_DIV1_SHIFT (0)
90#define SCG_SIRCDIV_DIV1_MASK ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT)
91/*
92 * FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK
93 * FIRC/SIRC DIV2 ==> xIRC_BUS_CLK
94 * FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK
95 */
96
97/* SCG Fast IRC Control Status Register */
98#define SCG_FIRC_CSR_FIRCVLD_SHIFT (24)
99#define SCG_FIRC_CSR_FIRCVLD_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT)
100
101#define SCG_FIRC_CSR_FIRCEN_SHIFT (0)
102#define SCG_FIRC_CSR_FIRCEN_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT)
103
104/* SCG Fast IRC Divide Register */
105#define SCG_FIRCDIV_DIV3_SHIFT (16)
106#define SCG_FIRCDIV_DIV3_MASK ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT)
107
108#define SCG_FIRCDIV_DIV2_SHIFT (8)
109#define SCG_FIRCDIV_DIV2_MASK ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT)
110
111#define SCG_FIRCDIV_DIV1_SHIFT (0)
112#define SCG_FIRCDIV_DIV1_MASK ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT)
113
114#define SCG_FIRCCFG_RANGE_SHIFT (0)
115#define SCG_FIRCCFG_RANGE_MASK ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT)
116
117#define SCG_FIRCCFG_RANGE_SHIFT (0)
118#define SCG_FIRCCFG_RANGE_48M ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT)
119
120/* SCG System OSC Control Status Register */
121#define SCG_SOSC_CSR_SOSCVLD_SHIFT (24)
122#define SCG_SOSC_CSR_SOSCVLD_MASK ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT)
123
124/* SCG Fast IRC Divide Register */
125#define SCG_SOSCDIV_DIV3_SHIFT (16)
126#define SCG_SOSCDIV_DIV3_MASK ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT)
127
128#define SCG_SOSCDIV_DIV2_SHIFT (8)
129#define SCG_SOSCDIV_DIV2_MASK ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT)
130
131#define SCG_SOSCDIV_DIV1_SHIFT (0)
132#define SCG_SOSCDIV_DIV1_MASK ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT)
133
134/* SCG RTC OSC Control Status Register */
135#define SCG_ROSC_CSR_ROSCVLD_SHIFT (24)
136#define SCG_ROSC_CSR_ROSCVLD_MASK ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT)
137
138#define SCG_SPLL_CSR_SPLLVLD_SHIFT (24)
139#define SCG_SPLL_CSR_SPLLVLD_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT)
140#define SCG_SPLL_CSR_SPLLEN_SHIFT (0)
141#define SCG_SPLL_CSR_SPLLEN_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT)
142#define SCG_APLL_CSR_APLLEN_SHIFT (0)
143#define SCG_APLL_CSR_APLLEN_MASK (0x1UL)
144#define SCG_APLL_CSR_APLLVLD_MASK (0x01000000)
145
146#define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000)
147
148
149#define SCG_PLL_PFD3_GATE_MASK (0x80000000)
150#define SCG_PLL_PFD2_GATE_MASK (0x00800000)
151#define SCG_PLL_PFD1_GATE_MASK (0x00008000)
152#define SCG_PLL_PFD0_GATE_MASK (0x00000080)
153#define SCG_PLL_PFD3_VALID_MASK (0x40000000)
154#define SCG_PLL_PFD2_VALID_MASK (0x00400000)
155#define SCG_PLL_PFD1_VALID_MASK (0x00004000)
156#define SCG_PLL_PFD0_VALID_MASK (0x00000040)
157
158#define SCG_PLL_PFD0_FRAC_SHIFT (0)
159#define SCG_PLL_PFD0_FRAC_MASK ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT)
160#define SCG_PLL_PFD1_FRAC_SHIFT (8)
161#define SCG_PLL_PFD1_FRAC_MASK ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT)
162#define SCG_PLL_PFD2_FRAC_SHIFT (16)
163#define SCG_PLL_PFD2_FRAC_MASK ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT)
164#define SCG_PLL_PFD3_FRAC_SHIFT (24)
165#define SCG_PLL_PFD3_FRAC_MASK ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT)
166
167#define SCG_PLL_CFG_POSTDIV2_SHIFT (28)
168#define SCG_PLL_CFG_POSTDIV2_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT)
169#define SCG_PLL_CFG_POSTDIV1_SHIFT (24)
170#define SCG_PLL_CFG_POSTDIV1_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT)
171#define SCG_PLL_CFG_MULT_SHIFT (16)
172#define SCG1_SPLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
173#define SCG_APLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
174#define SCG_PLL_CFG_PFDSEL_SHIFT (14)
175#define SCG_PLL_CFG_PFDSEL_MASK ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT)
176#define SCG_PLL_CFG_PREDIV_SHIFT (8)
177#define SCG_PLL_CFG_PREDIV_MASK ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT)
178#define SCG_PLL_CFG_BYPASS_SHIFT (2)
179/* 0: SPLL, 1: bypass */
180#define SCG_PLL_CFG_BYPASS_MASK ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT)
181#define SCG_PLL_CFG_PLLSEL_SHIFT (1)
182/* 0: pll, 1: pfd */
183#define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT)
184#define SCG_PLL_CFG_CLKSRC_SHIFT (0)
185/* 0: Sys-OSC, 1: FIRC */
186#define SCG_PLL_CFG_CLKSRC_MASK ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT)
187#define SCG0_SPLL_CFG_MULT_SHIFT (17)
188/* 0: Multiplier = 20, 1: Multiplier = 22 */
189#define SCG0_SPLL_CFG_MULT_MASK ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT)
190
191#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6)
192#define PLL_USB_PWR_MASK (0x01 << 12)
193#define PLL_USB_ENABLE_MASK (0x01 << 13)
194#define PLL_USB_BYPASS_MASK (0x01 << 16)
195#define PLL_USB_REG_ENABLE_MASK (0x01 << 21)
196#define PLL_USB_DIV_SEL_MASK (0x07 << 22)
197#define PLL_USB_LOCK_MASK (0x01 << 31)
198
199enum scg_clk {
200 SCG_SOSC_CLK,
201 SCG_FIRC_CLK,
202 SCG_SIRC_CLK,
203 SCG_ROSC_CLK,
204 SCG_SIRC_DIV1_CLK,
205 SCG_SIRC_DIV2_CLK,
206 SCG_SIRC_DIV3_CLK,
207 SCG_FIRC_DIV1_CLK,
208 SCG_FIRC_DIV2_CLK,
209 SCG_FIRC_DIV3_CLK,
210 SCG_SOSC_DIV1_CLK,
211 SCG_SOSC_DIV2_CLK,
212 SCG_SOSC_DIV3_CLK,
213 SCG_CORE_CLK,
214 SCG_BUS_CLK,
215 SCG_SPLL_PFD0_CLK,
216 SCG_SPLL_PFD1_CLK,
217 SCG_SPLL_PFD2_CLK,
218 SCG_SPLL_PFD3_CLK,
219 SCG_DDR_CLK,
220 SCG_NIC0_CLK,
221 SCG_GPU_CLK,
222 SCG_NIC1_CLK,
223 SCG_NIC1_BUS_CLK,
224 SCG_NIC1_EXT_CLK,
225 SCG_APLL_PFD0_CLK,
226 SCG_APLL_PFD1_CLK,
227 SCG_APLL_PFD2_CLK,
228 SCG_APLL_PFD3_CLK,
229 USB_PLL_OUT,
230 MIPI_PLL_OUT
231};
232
233enum scg_sys_src {
234 SCG_SCS_SYS_OSC = 1,
235 SCG_SCS_SLOW_IRC,
236 SCG_SCS_FAST_IRC,
237 SCG_SCS_RTC_OSC,
238 SCG_SCS_AUX_PLL,
239 SCG_SCS_SYS_PLL,
240 SCG_SCS_USBPHY_PLL,
241};
242
243/* PLL supported by i.mx7ulp */
244enum pll_clocks {
245 PLL_M4_SPLL, /* M4 SPLL */
246 PLL_M4_APLL, /* M4 APLL*/
247 PLL_A7_SPLL, /* A7 SPLL */
248 PLL_A7_APLL, /* A7 APLL */
249 PLL_USB, /* USB PLL*/
250 PLL_MIPI, /* MIPI PLL */
251};
252
253typedef struct scg_regs {
254 u32 verid; /* VERSION_ID */
255 u32 param; /* PARAMETER */
256 u32 rsvd11[2];
257
258 u32 csr; /* Clock Status Register */
259 u32 rccr; /* Run Clock Control Register */
260 u32 vccr; /* VLPR Clock Control Register */
261 u32 hccr; /* HSRUN Clock Control Register */
262 u32 clkoutcnfg; /* SCG CLKOUT Configuration Register */
263 u32 rsvd12[3];
264 u32 ddrccr; /* SCG DDR Clock Control Register */
265 u32 rsvd13[3];
266 u32 nicccr; /* NIC Clock Control Register */
267 u32 niccsr; /* NIC Clock Status Register */
268 u32 rsvd10[46];
269
270 u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */
271 u32 soscdiv; /* System OSC Divide Register */
272 u32 sosccfg; /* System Oscillator Configuration Register */
273 u32 sosctest; /* System Oscillator Test Register */
274 u32 rsvd20[60];
275
276 u32 sirccsr; /* Slow IRC Control Status Register, offset 0x200 */
277 u32 sircdiv; /* Slow IRC Divide Register */
278 u32 sirccfg; /* Slow IRC Configuration Register */
279 u32 sirctrim; /* Slow IRC Trim Register */
280 u32 loptrim; /* Low Power Oscillator Trim Register */
281 u32 sirctest; /* Slow IRC Test Register */
282 u32 rsvd30[58];
283
284 u32 firccsr; /* Fast IRC Control Status Register, offset 0x300 */
285 u32 fircdiv;
286 u32 firccfg;
287 u32 firctcfg; /* Fast IRC Trim Configuration Register */
288 u32 firctriml; /* Fast IRC Trim Low Register */
289 u32 firctrimh;
290 u32 fircstat; /* Fast IRC Status Register */
291 u32 firctest; /* Fast IRC Test Register */
292 u32 rsvd40[56];
293
294 u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */
295 u32 rsvd50[63];
296
297 u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */
298 u32 aplldiv; /* Auxiliary PLL Divider Register */
299 u32 apllcfg; /* Auxiliary PLL Configuration Register */
300 u32 apllpfd; /* Auxiliary PLL PFD Register */
301 u32 apllnum; /* Auxiliary PLL Numerator Register */
302 u32 aplldenom; /* Auxiliary PLL Denominator Register */
303 u32 apllss; /* Auxiliary PLL Spread Spectrum Register */
304 u32 rsvd60[55];
305 u32 apllock_cnfg; /* Auxiliary PLL LOCK Configuration Register */
306 u32 rsvd61[1];
307
308 u32 spllcsr; /* System PLL Control Status Register, offset 0x600 */
309 u32 splldiv; /* System PLL Divide Register */
310 u32 spllcfg; /* System PLL Configuration Register */
311 u32 spllpfd; /* System PLL Test Register */
312 u32 spllnum; /* System PLL Numerator Register */
313 u32 splldenom; /* System PLL Denominator Register */
314 u32 spllss; /* System PLL Spread Spectrum Register */
315 u32 rsvd70[55];
316 u32 spllock_cnfg; /* System PLL LOCK Configuration Register */
317 u32 rsvd71[1];
318
319 u32 upllcsr; /* USB PLL Control Status Register, offset 0x700 */
320 u32 uplldiv; /* USB PLL Divide Register */
321 u32 upllcfg; /* USB PLL Configuration Register */
322} scg_t, *scg_p;
323
324u32 scg_clk_get_rate(enum scg_clk clk);
325int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
326int scg_enable_usb_pll(bool usb_control);
327u32 decode_pll(enum pll_clocks pll);
328
329void scg_a7_rccr_init(void);
330void scg_a7_spll_init(void);
331void scg_a7_ddrclk_init(void);
Peng Fan684ccd92017-02-22 16:21:42 +0800[diff] [blame]332void scg_a7_firc_init(void);
333void scg_a7_nicclk_init(void);
334void scg_a7_sys_clk_sel(enum scg_sys_src clk);
335void scg_a7_info(void);
336void scg_a7_soscdiv_init(void);
Ye Li73df56a2019-07-22 01:25:08 +0000[diff] [blame]337void scg_a7_init_core_clk(void);
Peng Fan684ccd92017-02-22 16:21:42 +0800[diff] [blame]338
339#endif