blob: 4bfeb1df0488dc7aae25004db69f961787e3915e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Marek Vasutb938f382017-07-21 23:16:59 +02002/*
Marek Vasut2a8450f2023-01-26 21:01:32 +01003 * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car M3-W
Marek Vasutb938f382017-07-21 23:16:59 +02004 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2016 Cogent Embedded, Inc.
Marek Vasutb938f382017-07-21 23:16:59 +02007 */
8
9/dts-v1/;
Marek Vasutadaa0162020-04-04 16:12:48 +020010#include "r8a77960.dtsi"
Marek Vasut36f83d92017-09-12 23:01:51 +020011#include "ulcb.dtsi"
Marek Vasutb938f382017-07-21 23:16:59 +020012
13/ {
Marek Vasutadaa0162020-04-04 16:12:48 +020014 model = "Renesas M3ULCB board based on r8a77960";
Marek Vasutb938f382017-07-21 23:16:59 +020015 compatible = "renesas,m3ulcb", "renesas,r8a7796";
16
Marek Vasutb938f382017-07-21 23:16:59 +020017 memory@48000000 {
18 device_type = "memory";
19 /* first 128MB is reserved for secure area. */
20 reg = <0x0 0x48000000 0x0 0x38000000>;
21 };
Marek Vasutb938f382017-07-21 23:16:59 +020022
Marek Vasut36f83d92017-09-12 23:01:51 +020023 memory@600000000 {
24 device_type = "memory";
25 reg = <0x6 0x00000000 0x0 0x40000000>;
Marek Vasutb938f382017-07-21 23:16:59 +020026 };
27};
Marek Vasut07efb452017-11-29 04:27:36 +010028
29&du {
30 clocks = <&cpg CPG_MOD 724>,
31 <&cpg CPG_MOD 723>,
32 <&cpg CPG_MOD 722>,
Marek Vasut07efb452017-11-29 04:27:36 +010033 <&versaclock5 1>,
34 <&versaclock5 3>,
35 <&versaclock5 2>;
Marek Vasutfde558e2019-03-04 22:53:28 +010036 clock-names = "du.0", "du.1", "du.2",
Marek Vasut07efb452017-11-29 04:27:36 +010037 "dclkin.0", "dclkin.1", "dclkin.2";
38};