Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 29d247aa2a1f888836ec5a1282f6313cda44f5cf / . / arch / arm / dts / imx6qdl-gw52xx.dtsi
blob: f1d9ba1fac6a7026d764268cf977ecfe26c87852 [file] [log] [blame]
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
Tim Harveycf08d1b2021-03-01 14:33:35 -0800[diff] [blame]16 mmc0 = &usdhc3;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]17 nand = &gpmi;
18 ssi0 = &ssi1;
19 usb0 = &usbh1;
20 usb1 = &usbotg;
21 };
22
23 chosen {
24 bootargs = "console=ttymxc1,115200";
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm4 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <7>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 user-pb {
40 label = "user_pb";
41 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
42 linux,code = <BTN_0>;
43 };
44
45 user-pb1x {
46 label = "user_pb1x";
47 linux,code = <BTN_1>;
48 interrupt-parent = <&gsc>;
49 interrupts = <0>;
50 };
51
52 key-erased {
53 label = "key-erased";
54 linux,code = <BTN_2>;
55 interrupt-parent = <&gsc>;
56 interrupts = <1>;
57 };
58
59 eeprom-wp {
60 label = "eeprom_wp";
61 linux,code = <BTN_3>;
62 interrupt-parent = <&gsc>;
63 interrupts = <2>;
64 };
65
66 tamper {
67 label = "tamper";
68 linux,code = <BTN_4>;
69 interrupt-parent = <&gsc>;
70 interrupts = <5>;
71 };
72
73 switch-hold {
74 label = "switch_hold";
75 linux,code = <BTN_5>;
76 interrupt-parent = <&gsc>;
77 interrupts = <7>;
78 };
79 };
80
81 leds {
82 compatible = "gpio-leds";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_gpio_leds>;
85
86 led0: user1 {
87 label = "user1";
88 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
89 default-state = "on";
90 linux,default-trigger = "heartbeat";
91 };
92
93 led1: user2 {
94 label = "user2";
95 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
96 default-state = "off";
97 };
98
99 led2: user3 {
100 label = "user3";
101 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
102 default-state = "off";
103 };
104 };
105
106 memory@10000000 {
107 device_type = "memory";
108 reg = <0x10000000 0x20000000>;
109 };
110
111 pps {
112 compatible = "pps-gpio";
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_pps>;
115 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
116 status = "okay";
117 };
118
119 reg_1p0v: regulator-1p0v {
120 compatible = "regulator-fixed";
121 regulator-name = "1P0V";
122 regulator-min-microvolt = <1000000>;
123 regulator-max-microvolt = <1000000>;
124 regulator-always-on;
125 };
126
127 reg_3p3v: regulator-3p3v {
128 compatible = "regulator-fixed";
129 regulator-name = "3P3V";
130 regulator-min-microvolt = <3300000>;
131 regulator-max-microvolt = <3300000>;
132 regulator-always-on;
133 };
134
135 reg_5p0v: regulator-5p0v {
136 compatible = "regulator-fixed";
137 regulator-name = "5P0V";
138 regulator-min-microvolt = <5000000>;
139 regulator-max-microvolt = <5000000>;
140 regulator-always-on;
141 };
142
143 reg_usb_otg_vbus: regulator-usb-otg-vbus {
144 compatible = "regulator-fixed";
145 regulator-name = "usb_otg_vbus";
146 regulator-min-microvolt = <5000000>;
147 regulator-max-microvolt = <5000000>;
148 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
149 enable-active-high;
150 };
151
152 sound {
153 compatible = "fsl,imx6q-ventana-sgtl5000",
154 "fsl,imx-audio-sgtl5000";
155 model = "sgtl5000-audio";
156 ssi-controller = <&ssi1>;
157 audio-codec = <&codec>;
158 audio-routing =
159 "MIC_IN", "Mic Jack",
160 "Mic Jack", "Mic Bias",
161 "Headphone Jack", "HP_OUT";
162 mux-int-port = <1>;
163 mux-ext-port = <4>;
164 };
165};
166
167&audmux {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_audmux>;
170 status = "okay";
171};
172
173&can1 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_flexcan1>;
176 status = "okay";
177};
178
179&clks {
180 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
181 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
182 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
183 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
184};
185
186&ecspi3 {
187 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_ecspi3>;
190 status = "okay";
191};
192
193&fec {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_enet>;
196 phy-mode = "rgmii-id";
197 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
Tim Harvey6ce10d52021-05-03 11:21:27 -0700[diff] [blame]198 phy-reset-duration = <10>;
199 phy-reset-post-delay = <100>;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]200 status = "okay";
201};
202
203&gpmi {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_gpmi_nand>;
206 status = "okay";
207};
208
209&hdmi {
210 ddc-i2c-bus = <&i2c3>;
211 status = "okay";
212};
213
214&i2c1 {
215 clock-frequency = <100000>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_i2c1>;
218 status = "okay";
219
220 gsc: gsc@20 {
221 compatible = "gw,gsc";
222 reg = <0x20>;
223 interrupt-parent = <&gpio1>;
224 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
225 interrupt-controller;
226 #interrupt-cells = <1>;
227 #size-cells = <0>;
228
229 adc {
230 compatible = "gw,gsc-adc";
231 #address-cells = <1>;
232 #size-cells = <0>;
233
234 channel@0 {
235 gw,mode = <0>;
236 reg = <0x00>;
237 label = "temp";
238 };
239
240 channel@2 {
241 gw,mode = <1>;
242 reg = <0x02>;
243 label = "vdd_vin";
244 };
245
246 channel@5 {
247 gw,mode = <1>;
248 reg = <0x05>;
249 label = "vdd_3p3";
250 };
251
252 channel@8 {
253 gw,mode = <1>;
254 reg = <0x08>;
255 label = "vdd_bat";
256 };
257
258 channel@b {
259 gw,mode = <1>;
260 reg = <0x0b>;
261 label = "vdd_5p0";
262 };
263
264 channel@e {
265 gw,mode = <1>;
266 reg = <0xe>;
267 label = "vdd_arm";
268 };
269
270 channel@11 {
271 gw,mode = <1>;
272 reg = <0x11>;
273 label = "vdd_soc";
274 };
275
276 channel@14 {
277 gw,mode = <1>;
278 reg = <0x14>;
279 label = "vdd_3p0";
280 };
281
282 channel@17 {
283 gw,mode = <1>;
284 reg = <0x17>;
285 label = "vdd_1p5";
286 };
287
288 channel@1d {
289 gw,mode = <1>;
290 reg = <0x1d>;
291 label = "vdd_1p8";
292 };
293
294 channel@20 {
295 gw,mode = <1>;
296 reg = <0x20>;
297 label = "vdd_1p0";
298 };
299
300 channel@23 {
301 gw,mode = <1>;
302 reg = <0x23>;
303 label = "vdd_2p5";
304 };
305
306 channel@29 {
307 gw,mode = <1>;
308 reg = <0x29>;
309 label = "vdd_an1";
310 };
311 };
312 };
313
314 gsc_gpio: gpio@23 {
315 compatible = "nxp,pca9555";
316 reg = <0x23>;
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupt-parent = <&gsc>;
320 interrupts = <4>;
321 };
322
323 eeprom1: eeprom@50 {
324 compatible = "atmel,24c02";
325 reg = <0x50>;
326 pagesize = <16>;
327 };
328
329 eeprom2: eeprom@51 {
330 compatible = "atmel,24c02";
331 reg = <0x51>;
332 pagesize = <16>;
333 };
334
335 eeprom3: eeprom@52 {
336 compatible = "atmel,24c02";
337 reg = <0x52>;
338 pagesize = <16>;
339 };
340
341 eeprom4: eeprom@53 {
342 compatible = "atmel,24c02";
343 reg = <0x53>;
344 pagesize = <16>;
345 };
346
347 rtc: ds1672@68 {
348 compatible = "dallas,ds1672";
349 reg = <0x68>;
350 };
351};
352
353&i2c2 {
354 clock-frequency = <100000>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_i2c2>;
357 status = "okay";
358
359 ltc3676: pmic@3c {
360 compatible = "lltc,ltc3676";
361 reg = <0x3c>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_pmic>;
364 interrupt-parent = <&gpio1>;
365 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
366
367 regulators {
368 /* VDD_SOC (1+R1/R2 = 1.635) */
369 reg_vdd_soc: sw1 {
370 regulator-name = "vddsoc";
371 regulator-min-microvolt = <674400>;
372 regulator-max-microvolt = <1308000>;
373 lltc,fb-voltage-divider = <127000 200000>;
374 regulator-ramp-delay = <7000>;
375 regulator-boot-on;
376 regulator-always-on;
377 };
378
379 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
380 reg_1p8v: sw2 {
381 regulator-name = "vdd1p8";
382 regulator-min-microvolt = <1033310>;
383 regulator-max-microvolt = <2004000>;
384 lltc,fb-voltage-divider = <301000 200000>;
385 regulator-ramp-delay = <7000>;
386 regulator-boot-on;
387 regulator-always-on;
388 };
389
390 /* VDD_ARM (1+R1/R2 = 1.635) */
391 reg_vdd_arm: sw3 {
392 regulator-name = "vddarm";
393 regulator-min-microvolt = <674400>;
394 regulator-max-microvolt = <1308000>;
395 lltc,fb-voltage-divider = <127000 200000>;
396 regulator-ramp-delay = <7000>;
397 regulator-boot-on;
398 regulator-always-on;
399 };
400
401 /* VDD_DDR (1+R1/R2 = 2.105) */
402 reg_vdd_ddr: sw4 {
403 regulator-name = "vddddr";
404 regulator-min-microvolt = <868310>;
405 regulator-max-microvolt = <1684000>;
406 lltc,fb-voltage-divider = <221000 200000>;
407 regulator-ramp-delay = <7000>;
408 regulator-boot-on;
409 regulator-always-on;
410 };
411
412 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
413 reg_2p5v: ldo2 {
414 regulator-name = "vdd2p5";
415 regulator-min-microvolt = <2490375>;
416 regulator-max-microvolt = <2490375>;
417 lltc,fb-voltage-divider = <487000 200000>;
418 regulator-boot-on;
419 regulator-always-on;
420 };
421
422 /* VDD_AUD_1P8: Audio codec */
423 reg_aud_1p8v: ldo3 {
424 regulator-name = "vdd1p8a";
425 regulator-min-microvolt = <1800000>;
426 regulator-max-microvolt = <1800000>;
427 regulator-boot-on;
428 };
429
430 /* VDD_HIGH (1+R1/R2 = 4.17) */
431 reg_3p0v: ldo4 {
432 regulator-name = "vdd3p0";
433 regulator-min-microvolt = <3023250>;
434 regulator-max-microvolt = <3023250>;
435 lltc,fb-voltage-divider = <634000 200000>;
436 regulator-boot-on;
437 regulator-always-on;
438 };
439 };
440 };
441};
442
443&i2c3 {
444 clock-frequency = <100000>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_i2c3>;
447 status = "okay";
448
449 codec: sgtl5000@a {
450 compatible = "fsl,sgtl5000";
451 reg = <0x0a>;
452 clocks = <&clks IMX6QDL_CLK_CKO>;
453 VDDA-supply = <&reg_1p8v>;
454 VDDIO-supply = <&reg_3p3v>;
455 };
456
457 touchscreen: egalax_ts@4 {
458 compatible = "eeti,egalax_ts";
459 reg = <0x04>;
460 interrupt-parent = <&gpio7>;
461 interrupts = <12 2>;
462 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
463 };
464
465 accel@1e {
466 compatible = "nxp,fxos8700";
467 reg = <0x1e>;
468 };
469};
470
471&ldb {
472 status = "okay";
473
474 lvds-channel@0 {
475 fsl,data-mapping = "spwg";
476 fsl,data-width = <18>;
477 status = "okay";
478
479 display-timings {
480 native-mode = <&timing0>;
481 timing0: hsd100pxn1 {
482 clock-frequency = <65000000>;
483 hactive = <1024>;
484 vactive = <768>;
485 hback-porch = <220>;
486 hfront-porch = <40>;
487 vback-porch = <21>;
488 vfront-porch = <7>;
489 hsync-len = <60>;
490 vsync-len = <10>;
491 };
492 };
493 };
494};
495
496&pcie {
497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_pcie>;
499 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
500 status = "okay";
501};
502
503&pwm2 {
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
506 status = "disabled";
507};
508
509&pwm3 {
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
512 status = "disabled";
513};
514
515&pwm4 {
516 #pwm-cells = <2>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_pwm4>;
519 status = "okay";
520};
521
522&ssi1 {
523 status = "okay";
524};
525
526&uart1 {
527 pinctrl-names = "default";
528 pinctrl-0 = <&pinctrl_uart1>;
529 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
530 status = "okay";
531};
532
533&uart2 {
534 pinctrl-names = "default";
535 pinctrl-0 = <&pinctrl_uart2>;
536 status = "okay";
537};
538
539&uart5 {
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_uart5>;
542 status = "okay";
543};
544
545&usbotg {
546 vbus-supply = <&reg_usb_otg_vbus>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_usbotg>;
549 disable-over-current;
Tim Harvey3deb9892021-03-01 14:33:31 -0800[diff] [blame]550 dr_mode = "otg";
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]551 status = "okay";
552};
553
554&usbh1 {
555 status = "okay";
556};
557
558&usdhc3 {
559 pinctrl-names = "default", "state_100mhz", "state_200mhz";
560 pinctrl-0 = <&pinctrl_usdhc3>;
561 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
562 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
563 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
564 vmmc-supply = <&reg_3p3v>;
565 no-1-8-v; /* firmware will remove if board revision supports */
566 status = "okay";
567};
568
569&wdog1 {
570 pinctrl-names = "default";
571 pinctrl-0 = <&pinctrl_wdog>;
572 fsl,ext-reset-output;
573};
574
575&iomuxc {
576 pinctrl_audmux: audmuxgrp {
577 fsl,pins = <
578 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
579 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
580 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
581 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
582 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
583 >;
584 };
585
586 pinctrl_ecspi3: escpi3grp {
587 fsl,pins = <
588 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
589 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
590 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
591 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
592 >;
593 };
594
595 pinctrl_enet: enetgrp {
596 fsl,pins = <
597 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
598 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
599 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
600 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
601 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
602 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
603 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
604 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
605 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
606 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
607 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
608 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
609 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
610 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
611 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
612 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
613 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
614 >;
615 };
616
617 pinctrl_flexcan1: flexcan1grp {
618 fsl,pins = <
619 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
620 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
621 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
622 >;
623 };
624
625 pinctrl_gpio_leds: gpioledsgrp {
626 fsl,pins = <
627 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
628 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
629 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
630 >;
631 };
632
633 pinctrl_gpmi_nand: gpminandgrp {
634 fsl,pins = <
635 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
636 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
637 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
638 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
639 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
640 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
641 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
642 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
643 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
644 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
645 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
646 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
647 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
648 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
649 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
650 >;
651 };
652
653 pinctrl_i2c1: i2c1grp {
654 fsl,pins = <
655 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
656 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
657 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
658 >;
659 };
660
661 pinctrl_i2c2: i2c2grp {
662 fsl,pins = <
663 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
664 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
665 >;
666 };
667
668 pinctrl_i2c3: i2c3grp {
669 fsl,pins = <
670 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
671 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
672 >;
673 };
674
675 pinctrl_pcie: pciegrp {
676 fsl,pins = <
677 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
678 >;
679 };
680
681 pinctrl_pmic: pmicgrp {
682 fsl,pins = <
683 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
684 >;
685 };
686
687 pinctrl_pps: ppsgrp {
688 fsl,pins = <
689 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
690 >;
691 };
692
693 pinctrl_pwm2: pwm2grp {
694 fsl,pins = <
695 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
696 >;
697 };
698
699 pinctrl_pwm3: pwm3grp {
700 fsl,pins = <
701 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
702 >;
703 };
704
705 pinctrl_pwm4: pwm4grp {
706 fsl,pins = <
707 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
708 >;
709 };
710
711 pinctrl_uart1: uart1grp {
712 fsl,pins = <
713 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
714 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
715 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
716 >;
717 };
718
719 pinctrl_uart2: uart2grp {
720 fsl,pins = <
721 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
722 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
723 >;
724 };
725
726 pinctrl_uart5: uart5grp {
727 fsl,pins = <
728 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
729 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
730 >;
731 };
732
733 pinctrl_usbotg: usbotggrp {
734 fsl,pins = <
735 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
736 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
737 >;
738 };
739
740 pinctrl_usdhc3: usdhc3grp {
741 fsl,pins = <
742 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
743 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
744 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
745 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
746 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
747 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
748 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
749 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
750 >;
751 };
752
753 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
754 fsl,pins = <
755 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
756 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
757 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
758 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
759 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
760 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
761 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
762 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
763 >;
764 };
765
766 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
767 fsl,pins = <
768 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
769 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
770 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
771 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
772 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
773 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
774 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
775 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
776 >;
777 };
778
779 pinctrl_wdog: wdoggrp {
780 fsl,pins = <
781 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
782 >;
783 };
784};