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git01.mediatek.com / filogic / uboot / b676af2713e33d930f232580aa3f49c84cfef28b / . / drivers / clk / stm32 / clk-stm32mp25.c
blob: 043dd2273e19bafcfa476ca9900e50bdff652d06 [file] [log] [blame]
Gabriel Fernandezb676af22025-05-27 15:27:44 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
4 */
5
6#include <clk-uclass.h>
7#include <dm.h>
8#include <dt-bindings/clock/st,stm32mp25-rcc.h>
9#include <linux/clk-provider.h>
10#include <linux/io.h>
11
12#include "clk-stm32-core.h"
13#include "stm32mp25_rcc.h"
14
15/* Clock security definition */
16#define SECF_NONE -1
17
18static const char * const adc12_src[] = {
19 "ck_flexgen_46", "ck_icn_ls_mcu"
20};
21
22static const char * const adc3_src[] = {
23 "ck_flexgen_47", "ck_icn_ls_mcu", "ck_flexgen_46"
24};
25
26static const char * const usb2phy1_src[] = {
27 "ck_flexgen_57", "hse_div2_ck"
28};
29
30static const char * const usb2phy2_src[] = {
31 "ck_flexgen_58", "hse_div2_ck"
32};
33
34static const char * const usb3pciphy_src[] = {
35 "ck_flexgen_34", "hse_div2_ck"
36};
37
38static const char * const dsiblane_src[] = {
39 "txbyteclk", "ck_ker_ltdc"
40};
41
42static const char * const dsiphy_src[] = {
43 "ck_flexgen_28", "hse_ck"
44};
45
46static const char * const lvdsphy_src[] = {
47 "ck_flexgen_32", "hse_ck"
48};
49
50static const char * const dts_src[] = {
51 "hsi_ck", "hse_ck", "msi_ck"
52};
53
54static const char * const mco1_src[] = {
55 "ck_flexgen_61", "ck_obs0"
56};
57
58static const char * const mco2_src[] = {
59 "ck_flexgen_62", "ck_obs1"
60};
61
62enum enum_mux_cfg {
63 MUX_MCO1,
64 MUX_MCO2,
65 MUX_ADC12,
66 MUX_ADC3,
67 MUX_USB2PHY1,
68 MUX_USB2PHY2,
69 MUX_USB3PCIEPHY,
70 MUX_DSIBLANE,
71 MUX_DSIPHY,
72 MUX_LVDSPHY,
73 MUX_DTS,
74 MUX_NB
75};
76
77#define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\
78 .num_parents = ARRAY_SIZE(src),\
79 .parent_names = src,\
80 .reg_off = (_offset),\
81 .shift = (_shift),\
82 .width = (_witdh),\
83}
84
85static const struct stm32_mux_cfg stm32mp25_muxes[MUX_NB] = {
86 MUX_CFG(MUX_ADC12, adc12_src, RCC_ADC12CFGR, 12, 1),
87 MUX_CFG(MUX_ADC3, adc3_src, RCC_ADC3CFGR, 12, 2),
88 MUX_CFG(MUX_DSIBLANE, dsiblane_src, RCC_DSICFGR, 12, 1),
89 MUX_CFG(MUX_DSIPHY, dsiphy_src, RCC_DSICFGR, 15, 1),
90 MUX_CFG(MUX_DTS, dts_src, RCC_DTSCFGR, 12, 2),
91 MUX_CFG(MUX_MCO1, mco1_src, RCC_MCO1CFGR, 0, 1),
92 MUX_CFG(MUX_MCO2, mco2_src, RCC_MCO2CFGR, 0, 1),
93 MUX_CFG(MUX_LVDSPHY, lvdsphy_src, RCC_LVDSCFGR, 15, 1),
94 MUX_CFG(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1),
95 MUX_CFG(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1),
96 MUX_CFG(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1),
97};
98
99enum enum_gate_cfg {
100 GATE_ADC12,
101 GATE_ADC3,
102 GATE_ADF1,
103 GATE_CCI,
104 GATE_CRC,
105 GATE_CRYP1,
106 GATE_CRYP2,
107 GATE_CSI,
108 GATE_DBG,
109 GATE_DCMIPP,
110 GATE_DSI,
111 GATE_DTS,
112 GATE_ETH1,
113 GATE_ETH1MAC,
114 GATE_ETH1RX,
115 GATE_ETH1STP,
116 GATE_ETH1TX,
117 GATE_ETH2,
118 GATE_ETH2MAC,
119 GATE_ETH2RX,
120 GATE_ETH2STP,
121 GATE_ETH2TX,
122 GATE_ETHSW,
123 GATE_ETHSWMAC,
124 GATE_ETHSWREF,
125 GATE_ETR,
126 GATE_FDCAN,
127 GATE_GPU,
128 GATE_HASH,
129 GATE_HDP,
130 GATE_I2C1,
131 GATE_I2C2,
132 GATE_I2C3,
133 GATE_I2C4,
134 GATE_I2C5,
135 GATE_I2C6,
136 GATE_I2C7,
137 GATE_I2C8,
138 GATE_I3C1,
139 GATE_I3C2,
140 GATE_I3C3,
141 GATE_I3C4,
142 GATE_IS2M,
143 GATE_IWDG1,
144 GATE_IWDG2,
145 GATE_IWDG3,
146 GATE_IWDG4,
147 GATE_IWDG5,
148 GATE_LPTIM1,
149 GATE_LPTIM2,
150 GATE_LPTIM3,
151 GATE_LPTIM4,
152 GATE_LPTIM5,
153 GATE_LPUART1,
154 GATE_LTDC,
155 GATE_LVDS,
156 GATE_MCO1,
157 GATE_MCO2,
158 GATE_MDF1,
159 GATE_OSPI1,
160 GATE_OSPI2,
161 GATE_OSPIIOM,
162 GATE_PCIE,
163 GATE_PKA,
164 GATE_RNG,
165 GATE_SAES,
166 GATE_SAI1,
167 GATE_SAI2,
168 GATE_SAI3,
169 GATE_SAI4,
170 GATE_SDMMC1,
171 GATE_SDMMC2,
172 GATE_SDMMC3,
173 GATE_SERC,
174 GATE_SPDIFRX,
175 GATE_SPI1,
176 GATE_SPI2,
177 GATE_SPI3,
178 GATE_SPI4,
179 GATE_SPI5,
180 GATE_SPI6,
181 GATE_SPI7,
182 GATE_SPI8,
183 GATE_STGEN,
184 GATE_STM500,
185 GATE_TIM1,
186 GATE_TIM2,
187 GATE_TIM3,
188 GATE_TIM4,
189 GATE_TIM5,
190 GATE_TIM6,
191 GATE_TIM7,
192 GATE_TIM8,
193 GATE_TIM10,
194 GATE_TIM11,
195 GATE_TIM12,
196 GATE_TIM13,
197 GATE_TIM14,
198 GATE_TIM15,
199 GATE_TIM16,
200 GATE_TIM17,
201 GATE_TIM20,
202 GATE_TRACE,
203 GATE_UART4,
204 GATE_UART5,
205 GATE_UART7,
206 GATE_UART8,
207 GATE_UART9,
208 GATE_USART1,
209 GATE_USART2,
210 GATE_USART3,
211 GATE_USART6,
212 GATE_USBH,
213 GATE_USB2PHY1,
214 GATE_USB2PHY2,
215 GATE_USB3DR,
216 GATE_USB3PCIEPHY,
217 GATE_USBTC,
218 GATE_VDEC,
219 GATE_VENC,
220 GATE_VREF,
221 GATE_WWDG1,
222 GATE_WWDG2,
223 GATE_NB
224};
225
226#define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\
227 .reg_off = (_offset),\
228 .bit_idx = (_bit_idx),\
229 .set_clr = (_offset_clr),\
230}
231
232static const struct stm32_gate_cfg stm32mp25_gates[GATE_NB] = {
233 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0),
234 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0),
235 GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0),
236 GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0),
237 GATE_CFG(GATE_DBG, RCC_DBGCFGR, 8, 0),
238 GATE_CFG(GATE_TRACE, RCC_DBGCFGR, 9, 0),
239 GATE_CFG(GATE_STM500, RCC_STM500CFGR, 1, 0),
240 GATE_CFG(GATE_ETR, RCC_ETRCFGR, 1, 0),
241 GATE_CFG(GATE_IS2M, RCC_IS2MCFGR, 1, 0),
242 GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0),
243 GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0),
244 GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0),
245 GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0),
246 GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0),
247 GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0),
248 GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0),
249 GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0),
250 GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0),
251 GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0),
252 GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0),
253 GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0),
254 GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0),
255 GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0),
256 GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0),
257 GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0),
258 GATE_CFG(GATE_TIM20, RCC_TIM20CFGR, 1, 0),
259 GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0),
260 GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0),
261 GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0),
262 GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0),
263 GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0),
264 GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0),
265 GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0),
266 GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0),
267 GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0),
268 GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0),
269 GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0),
270 GATE_CFG(GATE_SPI7, RCC_SPI7CFGR, 1, 0),
271 GATE_CFG(GATE_SPI8, RCC_SPI8CFGR, 1, 0),
272 GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0),
273 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
274 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0),
275 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0),
276 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0),
277 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
278 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
279 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
280 GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0),
281 GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0),
282 GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0),
283 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
284 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
285 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
286 GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0),
287 GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0),
288 GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0),
289 GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0),
290 GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0),
291 GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0),
292 GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0),
293 GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0),
294 GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0),
295 GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0),
296 GATE_CFG(GATE_ADF1, RCC_ADF1CFGR, 1, 0),
297 GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0),
298 GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0),
299 GATE_CFG(GATE_ADC12, RCC_ADC12CFGR, 1, 0),
300 GATE_CFG(GATE_ADC3, RCC_ADC3CFGR, 1, 0),
301 GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0),
302 GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0),
303 GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0),
304 GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0),
305 GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0),
306 GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0),
307 GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0),
308 GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0),
309 GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0),
310 GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0),
311 GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0),
312 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0),
313 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0),
314 GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0),
315 GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0),
316 GATE_CFG(GATE_PCIE, RCC_PCIECFGR, 1, 0),
317 GATE_CFG(GATE_USBTC, RCC_UCPDCFGR, 1, 0),
318 GATE_CFG(GATE_ETHSWMAC, RCC_ETHSWCFGR, 1, 0),
319 GATE_CFG(GATE_ETHSW, RCC_ETHSWCFGR, 5, 0),
320 GATE_CFG(GATE_ETHSWREF, RCC_ETHSWCFGR, 21, 0),
321 GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0),
322 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
323 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
324 GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0),
325 GATE_CFG(GATE_GPU, RCC_GPUCFGR, 1, 0),
326 GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0),
327 GATE_CFG(GATE_DSI, RCC_DSICFGR, 1, 0),
328 GATE_CFG(GATE_LVDS, RCC_LVDSCFGR, 1, 0),
329 GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0),
330 GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0),
331 GATE_CFG(GATE_CCI, RCC_CCICFGR, 1, 0),
332 GATE_CFG(GATE_VDEC, RCC_VDECCFGR, 1, 0),
333 GATE_CFG(GATE_VENC, RCC_VENCCFGR, 1, 0),
334 GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0),
335 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0),
336 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
337 GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0),
338 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
339 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
340 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
341 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
342 GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0),
343 GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0),
344 GATE_CFG(GATE_IWDG5, RCC_IWDG5CFGR, 1, 0),
345 GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0),
346 GATE_CFG(GATE_WWDG2, RCC_WWDG2CFGR, 1, 0),
347 GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0),
348 GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0),
349 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
350 GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0),
351 GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0),
352 GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0),
353 GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0),
354 GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0),
355 GATE_CFG(GATE_I3C4, RCC_I3C4CFGR, 1, 0),
356};
357
358#define STM32_COMPOSITE_NODIV(_id, _name, _flags, _sec_id, _gate_id, _mux_id)\
359 STM32_COMPOSITE(_id, _name, _flags, _sec_id, _gate_id, _mux_id, NO_STM32_DIV)
360
361static const struct clock_config stm32mp25_clock_cfg[] = {
362 /* ADC */
363 STM32_GATE(CK_BUS_ADC12, "ck_icn_p_adc12", "ck_icn_ls_mcu", 0, GATE_ADC12, SECF_NONE),
364 STM32_COMPOSITE_NODIV(CK_KER_ADC12, "ck_ker_adc12", 0, SECF_NONE, GATE_ADC12, MUX_ADC12),
365 STM32_GATE(CK_BUS_ADC3, "ck_icn_p_adc3", "ck_icn_ls_mcu", 0, GATE_ADC3, SECF_NONE),
366 STM32_COMPOSITE_NODIV(CK_KER_ADC3, "ck_ker_adc3", 0, SECF_NONE, GATE_ADC3, MUX_ADC3),
367
368 /* ADF */
369 STM32_GATE(CK_BUS_ADF1, "ck_icn_p_adf1", "ck_icn_ls_mcu", 0, GATE_ADF1, SECF_NONE),
370 STM32_GATE(CK_KER_ADF1, "ck_ker_adf1", "ck_flexgen_42", 0, GATE_ADF1, SECF_NONE),
371
372 /* Camera */
373 /* DCMI */
374 STM32_GATE(CK_BUS_CCI, "ck_icn_p_cci", "ck_icn_ls_mcu", 0, GATE_CCI, SECF_NONE),
375
376 /* CSI-HOST */
377 STM32_GATE(CK_BUS_CSI, "ck_icn_p_csi", "ck_icn_apb4", 0, GATE_CSI, SECF_NONE),
378 STM32_GATE(CK_KER_CSI, "ck_ker_csi", "ck_flexgen_29", 0, GATE_CSI, SECF_NONE),
379 STM32_GATE(CK_KER_CSITXESC, "ck_ker_csitxesc", "ck_flexgen_30", 0, GATE_CSI, SECF_NONE),
380
381 /* CSI-PHY */
382 STM32_GATE(CK_KER_CSIPHY, "ck_ker_csiphy", "ck_flexgen_31", 0, GATE_CSI, SECF_NONE),
383
384 /* DCMIPP */
385 STM32_GATE(CK_BUS_DCMIPP, "ck_icn_p_dcmipp", "ck_icn_apb4", 0, GATE_DCMIPP, SECF_NONE),
386
387 /* CRC */
388 STM32_GATE(CK_BUS_CRC, "ck_icn_p_crc", "ck_icn_ls_mcu", 0, GATE_CRC, SECF_NONE),
389
390 /* CRYP */
391 STM32_GATE(CK_BUS_CRYP1, "ck_icn_p_cryp1", "ck_icn_ls_mcu", 0, GATE_CRYP1, SECF_NONE),
392 STM32_GATE(CK_BUS_CRYP2, "ck_icn_p_cryp2", "ck_icn_ls_mcu", 0, GATE_CRYP2, SECF_NONE),
393
394 /* DBG & TRACE*/
395 STM32_GATE(CK_KER_TSDBG, "ck_ker_tsdbg", "ck_flexgen_43", 0, GATE_DBG, SECF_NONE),
396 STM32_GATE(CK_KER_TPIU, "ck_ker_tpiu", "ck_flexgen_44", 0, GATE_TRACE, SECF_NONE),
397 STM32_GATE(CK_BUS_SYSATB, "ck_sys_atb", "ck_flexgen_45", 0, GATE_DBG, SECF_NONE),
398 STM32_GATE(CK_BUS_ETR, "ck_icn_m_etr", "ck_flexgen_45", 0, GATE_ETR, SECF_NONE),
399
400 /* Display subsystem */
401 /* LTDC */
402 STM32_GATE(CK_BUS_LTDC, "ck_icn_p_ltdc", "ck_icn_apb4", 0, GATE_LTDC, SECF_NONE),
403 STM32_GATE(CK_KER_LTDC, "ck_ker_ltdc", "ck_flexgen_27", CLK_SET_RATE_PARENT,
404 GATE_LTDC, SECF_NONE),
405
406 /* DSI */
407 STM32_GATE(CK_BUS_DSI, "ck_icn_p_dsi", "ck_icn_apb4", 0, GATE_DSI, SECF_NONE),
408 STM32_COMPOSITE_NODIV(CK_KER_DSIBLANE, "clk_lanebyte", 0, SECF_NONE,
409 GATE_DSI, MUX_DSIBLANE),
410
411 /* LVDS */
412 STM32_GATE(CK_BUS_LVDS, "ck_icn_p_lvds", "ck_icn_apb4", 0, GATE_LVDS, SECF_NONE),
413
414 /* DSI PHY */
415 STM32_COMPOSITE_NODIV(CK_KER_DSIPHY, "ck_ker_dsiphy", 0, SECF_NONE, GATE_DSI, MUX_DSIPHY),
416
417 /* LVDS PHY */
418 STM32_COMPOSITE_NODIV(CK_KER_LVDSPHY, "ck_ker_lvdsphy", 0,
419 SECF_NONE, GATE_LVDS, MUX_LVDSPHY),
420
421 /* DTS */
422 STM32_COMPOSITE_NODIV(CK_KER_DTS, "ck_ker_dts", 0, SECF_NONE, GATE_DTS, MUX_DTS),
423
424 /* ETHERNET */
425 STM32_GATE(CK_BUS_ETH1, "ck_icn_p_eth1", "ck_icn_ls_mcu", 0, GATE_ETH1, SECF_NONE),
426 STM32_GATE(CK_ETH1_STP, "ck_ker_eth1stp", "ck_icn_ls_mcu", 0, GATE_ETH1STP, SECF_NONE),
427 STM32_GATE(CK_KER_ETH1, "ck_ker_eth1", "ck_flexgen_54", 0, GATE_ETH1, SECF_NONE),
428 STM32_GATE(CK_KER_ETH1, "ck_ker_eth1ptp", "ck_flexgen_56", 0, GATE_ETH1, SECF_NONE),
429 STM32_GATE(CK_ETH1_MAC, "ck_ker_eth1mac", "ck_icn_ls_mcu", 0, GATE_ETH1MAC, SECF_NONE),
430 STM32_GATE(CK_ETH1_TX, "ck_ker_eth1tx", "ck_icn_ls_mcu", 0, GATE_ETH1TX, SECF_NONE),
431 STM32_GATE(CK_ETH1_RX, "ck_ker_eth1rx", "ck_icn_ls_mcu", 0, GATE_ETH1RX, SECF_NONE),
432
433 STM32_GATE(CK_BUS_ETH2, "ck_icn_p_eth2", "ck_icn_ls_mcu", 0, GATE_ETH2, SECF_NONE),
434 STM32_GATE(CK_ETH2_STP, "ck_ker_eth2stp", "ck_icn_ls_mcu", 0, GATE_ETH2STP, SECF_NONE),
435 STM32_GATE(CK_KER_ETH2, "ck_ker_eth2", "ck_flexgen_54", 0, GATE_ETH2, SECF_NONE),
436 STM32_GATE(CK_KER_ETH2, "ck_ker_eth2ptp", "ck_flexgen_56", 0, GATE_ETH2, SECF_NONE),
437 STM32_GATE(CK_ETH2_MAC, "ck_ker_eth2mac", "ck_icn_ls_mcu", 0, GATE_ETH2MAC, SECF_NONE),
438 STM32_GATE(CK_ETH2_TX, "ck_ker_eth2tx", "ck_icn_ls_mcu", 0, GATE_ETH2TX, SECF_NONE),
439 STM32_GATE(CK_ETH2_RX, "ck_ker_eth2rx", "ck_icn_ls_mcu", 0, GATE_ETH2RX, SECF_NONE),
440
441 STM32_GATE(CK_BUS_ETHSW, "ck_icn_p_ethsw", "ck_icn_ls_mcu", 0, GATE_ETHSWMAC, SECF_NONE),
442 STM32_GATE(CK_KER_ETHSW, "ck_ker_ethsw", "ck_flexgen_54", 0, GATE_ETHSW, SECF_NONE),
443 STM32_GATE(CK_KER_ETHSWREF, "ck_ker_ethswref", "ck_flexgen_60", 0,
444 GATE_ETHSWREF, SECF_NONE),
445
446 /* FDCAN */
447 STM32_GATE(CK_BUS_FDCAN, "ck_icn_p_fdcan", "ck_icn_apb2", 0, GATE_FDCAN, SECF_NONE),
448 STM32_GATE(CK_KER_FDCAN, "ck_ker_fdcan", "ck_flexgen_26", 0, GATE_FDCAN, SECF_NONE),
449
450 /* GPU */
451 STM32_GATE(CK_BUS_GPU, "ck_icn_m_gpu", "ck_flexgen_59", 0, GATE_GPU, SECF_NONE),
452
453 /* HASH */
454 STM32_GATE(CK_BUS_HASH, "ck_icn_p_hash", "ck_icn_ls_mcu", 0, GATE_HASH, SECF_NONE),
455
456 /* HDP */
457 STM32_GATE(CK_BUS_HDP, "ck_icn_p_hdp", "ck_icn_apb3", 0, GATE_HDP, SECF_NONE),
458
459 /* I2C */
460 STM32_GATE(CK_KER_I2C1, "ck_ker_i2c1", "ck_flexgen_12", 0, GATE_I2C1, SECF_NONE),
461 STM32_GATE(CK_KER_I2C2, "ck_ker_i2c2", "ck_flexgen_12", 0, GATE_I2C2, SECF_NONE),
462 STM32_GATE(CK_KER_I2C3, "ck_ker_i2c3", "ck_flexgen_13", 0, GATE_I2C3, SECF_NONE),
463 STM32_GATE(CK_KER_I2C5, "ck_ker_i2c5", "ck_flexgen_13", 0, GATE_I2C5, SECF_NONE),
464 STM32_GATE(CK_KER_I2C4, "ck_ker_i2c4", "ck_flexgen_14", 0, GATE_I2C4, SECF_NONE),
465 STM32_GATE(CK_KER_I2C6, "ck_ker_i2c6", "ck_flexgen_14", 0, GATE_I2C6, SECF_NONE),
466 STM32_GATE(CK_KER_I2C7, "ck_ker_i2c7", "ck_flexgen_15", 0, GATE_I2C7, SECF_NONE),
467 STM32_GATE(CK_KER_I2C8, "ck_ker_i2c8", "ck_flexgen_38", 0, GATE_I2C8, SECF_NONE),
468
469 /* I3C */
470 STM32_GATE(CK_KER_I3C1, "ck_ker_i3c1", "ck_flexgen_12", 0, GATE_I3C1, SECF_NONE),
471 STM32_GATE(CK_KER_I3C2, "ck_ker_i3c2", "ck_flexgen_12", 0, GATE_I3C2, SECF_NONE),
472 STM32_GATE(CK_KER_I3C3, "ck_ker_i3c3", "ck_flexgen_13", 0, GATE_I3C3, SECF_NONE),
473 STM32_GATE(CK_KER_I3C4, "ck_ker_i3c4", "ck_flexgen_36", 0, GATE_I3C4, SECF_NONE),
474
475 /* I2S */
476 STM32_GATE(CK_BUS_IS2M, "ck_icn_p_is2m", "ck_icn_apb3", 0, GATE_IS2M, SECF_NONE),
477
478 /* IWDG */
479 STM32_GATE(CK_BUS_IWDG1, "ck_icn_p_iwdg1", "ck_icn_apb3", 0, GATE_IWDG1, SECF_NONE),
480 STM32_GATE(CK_BUS_IWDG2, "ck_icn_p_iwdg2", "ck_icn_apb3", 0, GATE_IWDG2, SECF_NONE),
481 STM32_GATE(CK_BUS_IWDG3, "ck_icn_p_iwdg3", "ck_icn_apb3", 0, GATE_IWDG3, SECF_NONE),
482 STM32_GATE(CK_BUS_IWDG4, "ck_icn_p_iwdg4", "ck_icn_apb3", 0, GATE_IWDG4, SECF_NONE),
483 STM32_GATE(CK_BUS_IWDG5, "ck_icn_p_iwdg5", "ck_icn_ls_mcu", 0, GATE_IWDG5, SECF_NONE),
484
485 /* LPTIM */
486 STM32_GATE(CK_KER_LPTIM1, "ck_ker_lptim1", "ck_flexgen_07", 0, GATE_LPTIM1, SECF_NONE),
487 STM32_GATE(CK_KER_LPTIM2, "ck_ker_lptim2", "ck_flexgen_07", 0, GATE_LPTIM2, SECF_NONE),
488 STM32_GATE(CK_KER_LPTIM3, "ck_ker_lptim3", "ck_flexgen_40", 0, GATE_LPTIM3, SECF_NONE),
489 STM32_GATE(CK_KER_LPTIM4, "ck_ker_lptim4", "ck_flexgen_41", 0, GATE_LPTIM4, SECF_NONE),
490 STM32_GATE(CK_KER_LPTIM5, "ck_ker_lptim5", "ck_flexgen_41", 0, GATE_LPTIM5, SECF_NONE),
491
492 /* LPUART */
493 STM32_GATE(CK_KER_LPUART1, "ck_ker_lpuart1", "ck_flexgen_39", 0, GATE_LPUART1, SECF_NONE),
494
495 /* MCO1 & MCO2 */
496 STM32_COMPOSITE_NODIV(CK_MCO1, "ck_mco1", 0, SECF_NONE, GATE_MCO1, MUX_MCO1),
497 STM32_COMPOSITE_NODIV(CK_MCO2, "ck_mco2", 0, SECF_NONE, GATE_MCO2, MUX_MCO2),
498
499 /* MDF */
500 STM32_GATE(CK_KER_MDF1, "ck_ker_mdf1", "ck_flexgen_23", 0, GATE_MDF1, SECF_NONE),
501
502 /* OCTOSPI */
503 STM32_GATE(CK_BUS_OSPI1, "ck_icn_s_ospi1,", "ck_icn_hs_mcu", 0, GATE_OSPI1, SECF_NONE),
504 STM32_GATE(CK_BUS_OTFD1, "ck_icn_p_otfd1,", "ck_icn_hs_mcu", 0, GATE_OSPI1, SECF_NONE),
505 STM32_GATE(CK_KER_OSPI1, "ck_ker_ospi1", "ck_flexgen_48", 0, GATE_OSPI1, SECF_NONE),
506 STM32_GATE(CK_BUS_OSPI2, "ck_icn_s_ospi2,", "ck_icn_hs_mcu", 0, GATE_OSPI2, SECF_NONE),
507 STM32_GATE(CK_BUS_OTFD2, "ck_icn_p_otfd2,", "ck_icn_hs_mcu", 0, GATE_OSPI2, SECF_NONE),
508 STM32_GATE(CK_KER_OSPI2, "ck_ker_ospi2", "ck_flexgen_49", 0, GATE_OSPI2, SECF_NONE),
509 STM32_GATE(CK_BUS_OSPIIOM, "ck_icn_p_ospiiom", "ck_icn_ls_mcu", 0, GATE_OSPIIOM, SECF_NONE),
510
511 /* PCIE */
512 STM32_GATE(CK_BUS_PCIE, "ck_icn_p_pcie", "ck_icn_ls_mcu", 0, GATE_PCIE, SECF_NONE),
513
514 /* PKA */
515 STM32_GATE(CK_BUS_PKA, "ck_icn_p_pka", "ck_icn_ls_mcu", 0, GATE_PKA, SECF_NONE),
516
517 /* RNG */
518 STM32_GATE(CK_BUS_RNG, "ck_icn_p_rng", "ck_icn_ls_mcu", CLK_IGNORE_UNUSED,
519 GATE_RNG, SECF_NONE),
520
521 /* SAES */
522 STM32_GATE(CK_BUS_SAES, "ck_icn_p_saes", "ck_icn_ls_mcu", 0, GATE_SAES, SECF_NONE),
523
524 /* SAI [1..4] */
525 STM32_GATE(CK_BUS_SAI1, "ck_icn_p_sai1", "ck_icn_apb2", 0, GATE_SAI1, SECF_NONE),
526 STM32_GATE(CK_BUS_SAI2, "ck_icn_p_sai2", "ck_icn_apb2", 0, GATE_SAI2, SECF_NONE),
527 STM32_GATE(CK_BUS_SAI3, "ck_icn_p_sai3", "ck_icn_apb2", 0, GATE_SAI3, SECF_NONE),
528 STM32_GATE(CK_BUS_SAI4, "ck_icn_p_sai4", "ck_icn_apb2", 0, GATE_SAI4, SECF_NONE),
529 STM32_GATE(CK_KER_SAI1, "ck_ker_sai1", "ck_flexgen_23", 0, GATE_SAI1, SECF_NONE),
530 STM32_GATE(CK_KER_SAI2, "ck_ker_sai2", "ck_flexgen_24", 0, GATE_SAI2, SECF_NONE),
531 STM32_GATE(CK_KER_SAI3, "ck_ker_sai3", "ck_flexgen_25", 0, GATE_SAI3, SECF_NONE),
532 STM32_GATE(CK_KER_SAI4, "ck_ker_sai4", "ck_flexgen_25", 0, GATE_SAI4, SECF_NONE),
533
534 /* SDMMC */
535 STM32_GATE(CK_KER_SDMMC1, "ck_ker_sdmmc1", "ck_flexgen_51", 0, GATE_SDMMC1, SECF_NONE),
536 STM32_GATE(CK_KER_SDMMC2, "ck_ker_sdmmc2", "ck_flexgen_52", 0, GATE_SDMMC2, SECF_NONE),
537 STM32_GATE(CK_KER_SDMMC3, "ck_ker_sdmmc3", "ck_flexgen_53", 0, GATE_SDMMC3, SECF_NONE),
538
539 /* SERC */
540 STM32_GATE(CK_BUS_SERC, "ck_icn_p_serc", "ck_icn_apb3", 0, GATE_SERC, SECF_NONE),
541
542 /* SPDIF */
543 STM32_GATE(CK_KER_SPDIFRX, "ck_ker_spdifrx", "ck_flexgen_11", 0, GATE_SPDIFRX, SECF_NONE),
544
545 /* SPI */
546 STM32_GATE(CK_KER_SPI1, "ck_ker_spi1", "ck_flexgen_16", 0, GATE_SPI1, SECF_NONE),
547 STM32_GATE(CK_KER_SPI2, "ck_ker_spi2", "ck_flexgen_10", 0, GATE_SPI2, SECF_NONE),
548 STM32_GATE(CK_KER_SPI3, "ck_ker_spi3", "ck_flexgen_10", 0, GATE_SPI3, SECF_NONE),
549 STM32_GATE(CK_KER_SPI4, "ck_ker_spi4", "ck_flexgen_17", 0, GATE_SPI4, SECF_NONE),
550 STM32_GATE(CK_KER_SPI5, "ck_ker_spi5", "ck_flexgen_17", 0, GATE_SPI5, SECF_NONE),
551 STM32_GATE(CK_KER_SPI6, "ck_ker_spi6", "ck_flexgen_18", 0, GATE_SPI6, SECF_NONE),
552 STM32_GATE(CK_KER_SPI7, "ck_ker_spi7", "ck_flexgen_18", 0, GATE_SPI7, SECF_NONE),
553 STM32_GATE(CK_KER_SPI8, "ck_ker_spi8", "ck_flexgen_37", 0, GATE_SPI8, SECF_NONE),
554
555 /* STGEN */
556 STM32_GATE(CK_KER_STGEN, "ck_ker_stgen", "ck_flexgen_33", CLK_IGNORE_UNUSED,
557 GATE_STGEN, SECF_NONE),
558
559 /* STM500 */
560 STM32_GATE(CK_BUS_STM500, "ck_icn_s_stm500", "ck_icn_ls_mcu", 0, GATE_STM500, SECF_NONE),
561
562 /* Timers */
563 STM32_GATE(CK_KER_TIM2, "ck_ker_tim2", "timg1_ck", 0, GATE_TIM2, SECF_NONE),
564 STM32_GATE(CK_KER_TIM3, "ck_ker_tim3", "timg1_ck", 0, GATE_TIM3, SECF_NONE),
565 STM32_GATE(CK_KER_TIM4, "ck_ker_tim4", "timg1_ck", 0, GATE_TIM4, SECF_NONE),
566 STM32_GATE(CK_KER_TIM5, "ck_ker_tim5", "timg1_ck", 0, GATE_TIM5, SECF_NONE),
567 STM32_GATE(CK_KER_TIM6, "ck_ker_tim6", "timg1_ck", 0, GATE_TIM6, SECF_NONE),
568 STM32_GATE(CK_KER_TIM7, "ck_ker_tim7", "timg1_ck", 0, GATE_TIM7, SECF_NONE),
569 STM32_GATE(CK_KER_TIM10, "ck_ker_tim10", "timg1_ck", 0, GATE_TIM10, SECF_NONE),
570 STM32_GATE(CK_KER_TIM11, "ck_ker_tim11", "timg1_ck", 0, GATE_TIM11, SECF_NONE),
571 STM32_GATE(CK_KER_TIM12, "ck_ker_tim12", "timg1_ck", 0, GATE_TIM12, SECF_NONE),
572 STM32_GATE(CK_KER_TIM13, "ck_ker_tim13", "timg1_ck", 0, GATE_TIM13, SECF_NONE),
573 STM32_GATE(CK_KER_TIM14, "ck_ker_tim14", "timg1_ck", 0, GATE_TIM14, SECF_NONE),
574
575 STM32_GATE(CK_KER_TIM1, "ck_ker_tim1", "timg2_ck", 0, GATE_TIM1, SECF_NONE),
576 STM32_GATE(CK_KER_TIM8, "ck_ker_tim8", "timg2_ck", 0, GATE_TIM8, SECF_NONE),
577 STM32_GATE(CK_KER_TIM15, "ck_ker_tim15", "timg2_ck", 0, GATE_TIM15, SECF_NONE),
578 STM32_GATE(CK_KER_TIM16, "ck_ker_tim16", "timg2_ck", 0, GATE_TIM16, SECF_NONE),
579 STM32_GATE(CK_KER_TIM17, "ck_ker_tim17", "timg2_ck", 0, GATE_TIM17, SECF_NONE),
580 STM32_GATE(CK_KER_TIM20, "ck_ker_tim20", "timg2_ck", 0, GATE_TIM20, SECF_NONE),
581
582 /* UART/USART */
583 STM32_GATE(CK_KER_USART2, "ck_ker_usart2", "ck_flexgen_08", 0, GATE_USART2, SECF_NONE),
584 STM32_GATE(CK_KER_UART4, "ck_ker_uart4", "ck_flexgen_08", 0, GATE_UART4, SECF_NONE),
585 STM32_GATE(CK_KER_USART3, "ck_ker_usart3", "ck_flexgen_09", 0, GATE_USART3, SECF_NONE),
586 STM32_GATE(CK_KER_UART5, "ck_ker_uart5", "ck_flexgen_09", 0, GATE_UART5, SECF_NONE),
587 STM32_GATE(CK_KER_USART1, "ck_ker_usart1", "ck_flexgen_19", 0, GATE_USART1, SECF_NONE),
588 STM32_GATE(CK_KER_USART6, "ck_ker_usart6", "ck_flexgen_20", 0, GATE_USART6, SECF_NONE),
589 STM32_GATE(CK_KER_UART7, "ck_ker_uart7", "ck_flexgen_21", 0, GATE_UART7, SECF_NONE),
590 STM32_GATE(CK_KER_UART8, "ck_ker_uart8", "ck_flexgen_21", 0, GATE_UART8, SECF_NONE),
591 STM32_GATE(CK_KER_UART9, "ck_ker_uart9", "ck_flexgen_22", 0, GATE_UART9, SECF_NONE),
592
593 /* USB2PHY1 */
594 STM32_COMPOSITE_NODIV(CK_KER_USB2PHY1, "ck_ker_usb2phy1", 0,
595 SECF_NONE, GATE_USB2PHY1, MUX_USB2PHY1),
596
597 /* USBH */
598 STM32_GATE(CK_BUS_USB2OHCI, "ck_icn_m_usb2ohci", "ck_icn_hsl", 0, GATE_USBH, SECF_NONE),
599 STM32_GATE(CK_BUS_USB2EHCI, "ck_icn_m_usb2ehci", "ck_icn_hsl", 0, GATE_USBH, SECF_NONE),
600
601 /* USB2PHY2 */
602 STM32_COMPOSITE_NODIV(CK_KER_USB2PHY2EN, "ck_ker_usb2phy2_en", 0,
603 SECF_NONE, GATE_USB2PHY2, MUX_USB2PHY2),
604
605 /* USB3 PCIe COMBOPHY */
606 STM32_GATE(CK_BUS_USB3PCIEPHY, "ck_icn_p_usb3pciephy", "ck_icn_apb4", 0,
607 GATE_USB3PCIEPHY, SECF_NONE),
608
609 STM32_COMPOSITE_NODIV(CK_KER_USB3PCIEPHY, "ck_ker_usb3pciephy", 0,
610 SECF_NONE, GATE_USB3PCIEPHY, MUX_USB3PCIEPHY),
611
612 /* USB3 DRD */
613 STM32_GATE(CK_BUS_USB3DR, "ck_icn_m_usb3dr", "ck_icn_hsl", 0, GATE_USB3DR, SECF_NONE),
614 STM32_GATE(CK_KER_USB2PHY2, "ck_ker_usb2phy2", "ck_flexgen_58", 0,
615 GATE_USB3DR, SECF_NONE),
616
617 /* UCPD */
618 STM32_GATE(CK_BUS_USBTC, "ck_icn_p_usbtc", "ck_flexgen_35", 0, GATE_USBTC, SECF_NONE),
619 STM32_GATE(CK_KER_USBTC, "ck_ker_usbtc", "ck_flexgen_35", 0, GATE_USBTC, SECF_NONE),
620
621 /* VDEC / VENC */
622 STM32_GATE(CK_BUS_VDEC, "ck_icn_p_vdec", "ck_icn_apb4", 0, GATE_VDEC, SECF_NONE),
623 STM32_GATE(CK_BUS_VENC, "ck_icn_p_venc", "ck_icn_apb4", 0, GATE_VENC, SECF_NONE),
624
625 /* VREF */
626 STM32_GATE(CK_BUS_VREF, "ck_icn_p_vref", "ck_icn_apb3", 0, RCC_VREFCFGR, SECF_NONE),
627
628 /* WWDG */
629 STM32_GATE(CK_BUS_WWDG1, "ck_icn_p_wwdg1", "ck_icn_apb3", 0, GATE_WWDG1, SECF_NONE),
630 STM32_GATE(CK_BUS_WWDG2, "ck_icn_p_wwdg2", "ck_icn_ls_mcu", 0, GATE_WWDG2, SECF_NONE),
631};
632
633static const struct stm32_clock_match_data stm32mp25_data = {
634 .tab_clocks = stm32mp25_clock_cfg,
635 .num_clocks = ARRAY_SIZE(stm32mp25_clock_cfg),
636 .clock_data = &(const struct clk_stm32_clock_data) {
637 .num_gates = ARRAY_SIZE(stm32mp25_gates),
638 .gates = stm32mp25_gates,
639 .muxes = stm32mp25_muxes,
640 },
641};
642
643static int stm32mp25_clk_probe(struct udevice *dev)
644{
645 fdt_addr_t base = dev_read_addr(dev->parent);
646 struct udevice *scmi;
647
648 if (base == FDT_ADDR_T_NONE)
649 return -EINVAL;
650
651 /* force SCMI probe to register all SCMI clocks */
652 uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(scmi_clock), &scmi);
653
654 stm32_rcc_init(dev, &stm32mp25_data);
655
656 return 0;
657}
658
659U_BOOT_DRIVER(stm32mp25_clock) = {
660 .name = "stm32mp25_clk",
661 .id = UCLASS_CLK,
662 .ops = &stm32_clk_ops,
663 .priv_auto = sizeof(struct stm32mp_rcc_priv),
664 .probe = stm32mp25_clk_probe,
665};