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git01.mediatek.com / filogic / uboot / 28debca01b71441e96bc2db34181924c3122e9e4 / . / include / configs / sama5d4ek.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]2/*
3 * Configuration settings for the SAMA5D4EK board.
4 *
5 * Copyright (C) 2014 Atmel
6 * Bo Shen <voice.shen@atmel.com>
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Wu, Josh42587542015-03-30 14:51:19 +0800[diff] [blame]12#include "at91-sama5_common.h"
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]13
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]14/* SDRAM */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]15#define CONFIG_SYS_SDRAM_BASE 0x20000000
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]16#define CONFIG_SYS_SDRAM_SIZE 0x20000000
17
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]18/* NAND flash */
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]19#ifdef CONFIG_CMD_NAND
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]20#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]21#define CONFIG_SYS_NAND_BASE 0x80000000
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]22/* our ALE is AD21 */
23#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
24/* our CLE is AD22 */
25#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]26#endif
27
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]28/* SPL */
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]29
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]30#define CONFIG_SYS_MONITOR_LEN (512 << 10)
31
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]32#endif