Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 1 | /* |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 2 | * U-Boot - Configuration file for BF537 STAMP board |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 3 | */ |
| 4 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 5 | #ifndef __CONFIG_BF537_STAMP_H__ |
| 6 | #define __CONFIG_BF537_STAMP_H__ |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 7 | |
Mike Frysinger | 18a407c | 2009-04-24 17:22:40 -0400 | [diff] [blame] | 8 | #include <asm/config-pre.h> |
Mike Frysinger | f0dd792 | 2008-02-18 05:26:48 -0500 | [diff] [blame] | 9 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 10 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 11 | /* |
| 12 | * Processor Settings |
| 13 | */ |
Mike Frysinger | 5b0c128 | 2010-12-23 14:58:37 -0500 | [diff] [blame] | 14 | #define CONFIG_BFIN_CPU bf537-0.2 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 16 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 17 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 18 | /* |
| 19 | * Clock Settings |
| 20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
| 21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
| 22 | */ |
| 23 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
| 24 | #define CONFIG_CLKIN_HZ 25000000 |
| 25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
| 26 | /* 1 = CLKIN / 2 */ |
| 27 | #define CONFIG_CLKIN_HALF 0 |
| 28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
| 29 | /* 1 = bypass PLL */ |
| 30 | #define CONFIG_PLL_BYPASS 0 |
| 31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
| 32 | /* Values can range from 0-63 (where 0 means 64) */ |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 33 | #define CONFIG_VCO_MULT 20 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 34 | /* CCLK_DIV controls the core clock divider */ |
| 35 | /* Values can be 1, 2, 4, or 8 ONLY */ |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 36 | #define CONFIG_CCLK_DIV 1 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 37 | /* SCLK_DIV controls the system clock divider */ |
| 38 | /* Values can range from 1-15 */ |
Mike Frysinger | 40069e1 | 2008-12-08 16:16:11 -0500 | [diff] [blame] | 39 | #define CONFIG_SCLK_DIV 4 |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 40 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 41 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 42 | /* |
| 43 | * Memory Settings |
| 44 | */ |
| 45 | #define CONFIG_MEM_ADD_WDTH 10 |
| 46 | #define CONFIG_MEM_SIZE 64 |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 47 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 48 | #define CONFIG_EBIU_SDRRC_VAL 0x306 |
| 49 | #define CONFIG_EBIU_SDGCTL_VAL 0x91114d |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 50 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 51 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF |
| 52 | #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 |
| 53 | #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 54 | |
Sonic Zhang | ae26b40 | 2013-02-20 18:05:16 +0800 | [diff] [blame] | 55 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 56 | #define CONFIG_SYS_MALLOC_LEN (384 * 1024) |
| 57 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 58 | |
| 59 | /* |
| 60 | * Network Settings |
| 61 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 62 | #ifndef __ADSPBF534__ |
| 63 | #define ADI_CMDS_NETWORK 1 |
| 64 | #define CONFIG_BFIN_MAC |
| 65 | #define CONFIG_NETCONSOLE 1 |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 66 | #endif |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 67 | #define CONFIG_HOSTNAME bf537-stamp |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 68 | |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 69 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 70 | * Flash Settings |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 71 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 72 | #define CONFIG_FLASH_CFI_DRIVER |
| 73 | #define CONFIG_SYS_FLASH_BASE 0x20000000 |
| 74 | #define CONFIG_SYS_FLASH_CFI |
| 75 | #define CONFIG_SYS_FLASH_PROTECTION |
| 76 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 77 | /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */ |
| 78 | #define CONFIG_SYS_MAX_FLASH_SECT 71 |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 79 | |
| 80 | |
| 81 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 82 | * SPI Settings |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 83 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 84 | #define CONFIG_BFIN_SPI |
| 85 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 |
Mike Frysinger | 9a440646 | 2009-06-14 22:29:35 -0400 | [diff] [blame] | 86 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
Mike Frysinger | cf01ec9 | 2010-09-19 16:26:55 -0400 | [diff] [blame] | 87 | #define CONFIG_SPI_FLASH_ALL |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 88 | |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 89 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 90 | /* |
| 91 | * Env Storage Settings |
| 92 | */ |
| 93 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
| 94 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
Vivi Li | 535ec1f | 2009-06-12 10:53:22 +0000 | [diff] [blame] | 95 | #define CONFIG_ENV_OFFSET 0x10000 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 96 | #define CONFIG_ENV_SIZE 0x2000 |
Vivi Li | 535ec1f | 2009-06-12 10:53:22 +0000 | [diff] [blame] | 97 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 98 | #else |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 99 | #define CONFIG_ENV_IS_IN_FLASH |
| 100 | #define CONFIG_ENV_OFFSET 0x4000 |
| 101 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
| 102 | #define CONFIG_ENV_SIZE 0x2000 |
| 103 | #define CONFIG_ENV_SECT_SIZE 0x2000 |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 104 | #endif |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 105 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) |
| 106 | #define ENV_IS_EMBEDDED |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 107 | #else |
Mike Frysinger | 45b57bd | 2009-07-21 22:17:36 -0400 | [diff] [blame] | 108 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 109 | #endif |
Mike Frysinger | 37f4870 | 2009-06-14 06:29:07 -0400 | [diff] [blame] | 110 | #ifdef ENV_IS_EMBEDDED |
| 111 | /* WARNING - the following is hand-optimized to fit within |
| 112 | * the sector before the environment sector. If it throws |
| 113 | * an error during compilation remove an object here to get |
| 114 | * it linked after the configuration sector. |
| 115 | */ |
| 116 | # define LDS_BOARD_TEXT \ |
Masahiro Yamada | 30a198b | 2013-11-11 14:36:00 +0900 | [diff] [blame] | 117 | arch/blackfin/lib/built-in.o (.text*); \ |
| 118 | arch/blackfin/cpu/built-in.o (.text*); \ |
Mike Frysinger | 37f4870 | 2009-06-14 06:29:07 -0400 | [diff] [blame] | 119 | . = DEFINED(env_offset) ? env_offset : .; \ |
Mike Frysinger | a0d6041 | 2010-11-19 19:28:56 -0500 | [diff] [blame] | 120 | common/env_embedded.o (.text*); |
Mike Frysinger | 37f4870 | 2009-06-14 06:29:07 -0400 | [diff] [blame] | 121 | #endif |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 122 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 123 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 124 | /* |
| 125 | * I2C Settings |
| 126 | */ |
Scott Jiang | 80d27fa | 2014-11-13 15:30:55 +0800 | [diff] [blame] | 127 | #define CONFIG_SYS_I2C |
Scott Jiang | 655761e | 2014-11-13 15:30:53 +0800 | [diff] [blame] | 128 | #define CONFIG_SYS_I2C_ADI |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 129 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 130 | |
| 131 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 132 | * SPI_MMC Settings |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 133 | */ |
Sonic Zhang | ae26b40 | 2013-02-20 18:05:16 +0800 | [diff] [blame] | 134 | #define CONFIG_MMC_SPI |
| 135 | #ifdef CONFIG_MMC_SPI |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 136 | #define CONFIG_MMC |
Mike Frysinger | aa5e922 | 2010-12-24 12:53:47 -0500 | [diff] [blame] | 137 | #define CONFIG_GENERIC_MMC |
Sonic Zhang | ae26b40 | 2013-02-20 18:05:16 +0800 | [diff] [blame] | 138 | #endif |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 139 | |
| 140 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 141 | * NAND Settings |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 142 | */ |
Mike Frysinger | c0e7c7a | 2009-05-25 22:42:28 -0400 | [diff] [blame] | 143 | /* #define CONFIG_NAND_PLAT */ |
Sonic Zhang | ae26b40 | 2013-02-20 18:05:16 +0800 | [diff] [blame] | 144 | #ifdef CONFIG_NAND_PLAT |
Mike Frysinger | c0e7c7a | 2009-05-25 22:42:28 -0400 | [diff] [blame] | 145 | #define CONFIG_SYS_NAND_BASE 0x20212000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 146 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 147 | |
Mike Frysinger | c0e7c7a | 2009-05-25 22:42:28 -0400 | [diff] [blame] | 148 | #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) |
| 149 | #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) |
Mike Frysinger | c0e7c7a | 2009-05-25 22:42:28 -0400 | [diff] [blame] | 150 | #define BFIN_NAND_WRITE(addr, cmd) \ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 151 | do { \ |
Mike Frysinger | c0e7c7a | 2009-05-25 22:42:28 -0400 | [diff] [blame] | 152 | bfin_write8(addr, cmd); \ |
| 153 | SSYNC(); \ |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 154 | } while (0) |
| 155 | |
Mike Frysinger | c0e7c7a | 2009-05-25 22:42:28 -0400 | [diff] [blame] | 156 | #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) |
| 157 | #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) |
Mike Frysinger | 0892b0c | 2010-07-05 04:55:05 -0400 | [diff] [blame] | 158 | #define NAND_PLAT_GPIO_DEV_READY GPIO_PF3 |
Sonic Zhang | ae26b40 | 2013-02-20 18:05:16 +0800 | [diff] [blame] | 159 | #endif /* CONFIG_NAND_PLAT */ |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 160 | |
| 161 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 162 | * CF-CARD IDE-HDD Support |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 163 | */ |
Michael Hennerich | ccb0d4e | 2009-06-18 09:12:50 +0000 | [diff] [blame] | 164 | |
| 165 | /* |
| 166 | * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card) |
| 167 | * Strange address mapping Blackfin A13 connects to CF_A0 |
| 168 | */ |
| 169 | |
| 170 | /* #define CONFIG_BFIN_TRUE_IDE */ |
| 171 | |
| 172 | /* |
| 173 | * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card) |
| 174 | * This should be the preferred mode |
| 175 | */ |
| 176 | |
| 177 | /* #define CONFIG_BFIN_CF_IDE */ |
| 178 | |
| 179 | /* |
| 180 | * Add IDE Disk Drive (HDD) support |
| 181 | * See example interface here: |
| 182 | * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin |
| 183 | */ |
| 184 | |
| 185 | /* #define CONFIG_BFIN_HDD_IDE */ |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 186 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 187 | #if defined(CONFIG_BFIN_CF_IDE) || \ |
| 188 | defined(CONFIG_BFIN_HDD_IDE) || \ |
| 189 | defined(CONFIG_BFIN_TRUE_IDE) |
| 190 | # define CONFIG_BFIN_IDE 1 |
| 191 | # define CONFIG_CMD_IDE |
| 192 | #endif |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 193 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 194 | #if defined(CONFIG_BFIN_IDE) |
| 195 | |
| 196 | #define CONFIG_DOS_PARTITION 1 |
| 197 | /* |
| 198 | * IDE/ATA stuff |
| 199 | */ |
| 200 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
| 201 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
| 202 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ |
| 203 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 204 | #define CONFIG_SYS_IDE_MAXBUS 1 |
| 205 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 206 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 207 | #undef CONFIG_EBIU_AMBCTL1_VAL |
| 208 | #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3 |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 209 | |
| 210 | #define CONFIG_CF_ATASEL_DIS 0x20311800 |
| 211 | #define CONFIG_CF_ATASEL_ENA 0x20311802 |
| 212 | |
| 213 | #if defined(CONFIG_BFIN_TRUE_IDE) |
| 214 | /* |
| 215 | * Note that these settings aren't for the most part used in include/ata.h |
| 216 | * when all of the ATA registers are setup |
| 217 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 218 | #define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000 |
| 219 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 220 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ |
| 221 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ |
| 222 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ |
Michael Hennerich | ccb0d4e | 2009-06-18 09:12:50 +0000 | [diff] [blame] | 223 | #define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */ |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 224 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 225 | #elif defined(CONFIG_BFIN_CF_IDE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 226 | #define CONFIG_SYS_ATA_BASE_ADDR 0x20211800 |
| 227 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 228 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */ |
| 229 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */ |
| 230 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */ |
Michael Hennerich | ccb0d4e | 2009-06-18 09:12:50 +0000 | [diff] [blame] | 231 | #define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */ |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 232 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 233 | #elif defined(CONFIG_BFIN_HDD_IDE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 234 | #define CONFIG_SYS_ATA_BASE_ADDR 0x20314000 |
| 235 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 236 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ |
| 237 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ |
| 238 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 239 | #define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */ |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 240 | #undef CONFIG_SCLK_DIV |
| 241 | #define CONFIG_SCLK_DIV 8 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 242 | #endif |
| 243 | |
| 244 | #endif |
| 245 | |
| 246 | |
| 247 | /* |
| 248 | * Misc Settings |
| 249 | */ |
| 250 | #define CONFIG_MISC_INIT_R |
| 251 | #define CONFIG_RTC_BFIN |
| 252 | #define CONFIG_UART_CONSOLE 0 |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 253 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 254 | /* Define if want to do post memory test */ |
| 255 | #undef CONFIG_POST |
| 256 | #ifdef CONFIG_POST |
Mike Frysinger | 8a4e187 | 2011-05-10 13:00:30 -0400 | [diff] [blame] | 257 | #define CONFIG_SYS_POST_HOTKEYS_GPIO GPIO_PF5 |
Mike Frysinger | 32ed1fe | 2011-05-10 16:22:25 -0400 | [diff] [blame] | 258 | #define CONFIG_POST_BSPEC1_GPIO_LEDS \ |
| 259 | GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, |
| 260 | #define CONFIG_POST_BSPEC2_GPIO_BUTTONS \ |
| 261 | GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2, |
| 262 | #define CONFIG_POST_BSPEC2_GPIO_NAMES \ |
| 263 | 10, 11, 12, 13, |
Mike Frysinger | 368cfc8 | 2011-05-10 16:48:36 -0400 | [diff] [blame] | 264 | #define CONFIG_SYS_POST_FLASH_START 11 |
| 265 | #define CONFIG_SYS_POST_FLASH_END 71 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 266 | #endif |
| 267 | |
Mike Frysinger | afd0fbf | 2010-01-21 23:29:18 -0500 | [diff] [blame] | 268 | /* These are for board tests */ |
| 269 | #if 0 |
| 270 | #define CONFIG_BOOTCOMMAND "bootldr 0x203f0100" |
Mike Frysinger | afd0fbf | 2010-01-21 23:29:18 -0500 | [diff] [blame] | 271 | #endif |
| 272 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 273 | |
| 274 | /* |
| 275 | * Pull in common ADI header for remaining command/environment setup |
| 276 | */ |
| 277 | #include <configs/bfin_adi_common.h> |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 278 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 279 | #endif |