| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Tom Warren | b7ea6d1 | 2014-01-24 12:46:13 -0700 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010-2013 |
| 4 | * NVIDIA Corporation <www.nvidia.com> |
| Tom Warren | b7ea6d1 | 2014-01-24 12:46:13 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _TEGRA124_GP_PADCTRL_H_ |
| 8 | #define _TEGRA124_GP_PADCTRL_H_ |
| 9 | |
| 10 | #include <asm/arch-tegra/gp_padctrl.h> |
| 11 | |
| 12 | /* APB_MISC_GP and padctrl registers */ |
| 13 | struct apb_misc_gp_ctlr { |
| 14 | u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ |
| 15 | u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ |
| 16 | u32 reserved0[22]; /* 0x08 - 0x5C: */ |
| 17 | u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ |
| 18 | u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ |
| 19 | u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ |
| 20 | u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ |
| 21 | u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ |
| 22 | u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ |
| 23 | u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ |
| 24 | u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ |
| 25 | u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ |
| 26 | u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ |
| 27 | u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ |
| 28 | u32 reserved1; /* 0x8C: */ |
| 29 | u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ |
| 30 | u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ |
| 31 | u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ |
| 32 | u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ |
| 33 | u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ |
| 34 | u32 reserved2[3]; /* 0xA4 - 0xAC: */ |
| 35 | u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ |
| 36 | u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ |
| 37 | u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ |
| 38 | u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ |
| 39 | u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ |
| 40 | u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ |
| 41 | u32 reserved3[9]; /* 0xC8-0xE8: */ |
| 42 | u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ |
| 43 | u32 reserved4[3]; /* 0xF0-0xF8: */ |
| 44 | u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ |
| 45 | u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ |
| 46 | u32 reserved5[3]; /* 0x104-0x10C: */ |
| 47 | u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ |
| 48 | u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ |
| 49 | u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ |
| 50 | u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ |
| 51 | u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ |
| 52 | u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ |
| 53 | u32 reserved6; /* 0x128: */ |
| 54 | u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ |
| 55 | u32 reserved7[2]; /* 0x130 - 0x134: */ |
| 56 | u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ |
| 57 | u32 reserved8[22]; /* 0x13C - 0x190: */ |
| 58 | u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ |
| 59 | u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ |
| 60 | u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ |
| 61 | u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ |
| 62 | u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ |
| 63 | u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ |
| 64 | u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ |
| 65 | }; |
| 66 | |
| 67 | /* SDMMC1/3 settings from section 27.5 of T114 TRM */ |
| 68 | #define SDIOCFG_DRVUP_SLWF 0 |
| 69 | #define SDIOCFG_DRVDN_SLWR 0 |
| 70 | #define SDIOCFG_DRVUP 0x24 |
| 71 | #define SDIOCFG_DRVDN 0x14 |
| 72 | |
| 73 | #endif /* _TEGRA124_GP_PADCTRL_H_ */ |