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git01.mediatek.com / filogic / uboot / 26f9a6c74e454f8fdd84f187cd789a45bf129e84 / . / board / stx / stxxtc / stxxtc.c
blob: 1996efb664d611ce6d8efb02e18231897940a660 [file] [log] [blame]
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]1/*
2 * (C) Copyright 2000-2004
3 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2005
6 * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]9 */
10
11/*
12 * U-Boot port on STx XTc board
13 * Mostly copied from Netta
14 */
15
16#include <common.h>
17#include <miiphy.h>
18
19#include "mpc8xx.h"
20
21#ifdef CONFIG_HW_WATCHDOG
22#include <watchdog.h>
23#endif
24
25/****************************************************************/
26
27/* some sane bit macros */
28#define _BD(_b) (1U << (31-(_b)))
29#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
30
31#define _BW(_b) (1U << (15-(_b)))
32#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
33
34#define _BB(_b) (1U << (7-(_b)))
35#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
36
37#define _B(_b) _BD(_b)
38#define _BR(_l, _h) _BDR(_l, _h)
39
40/****************************************************************/
41
42/*
43 * Check Board Identity:
44 *
45 * Return 1 always.
46 */
47
48int checkboard(void)
49{
50 printf ("Silicon Turnkey eXpress XTc\n");
51 return (0);
52}
53
54/****************************************************************/
55
56#define _NOT_USED_ 0xFFFFFFFF
57
58/****************************************************************/
59
60#define CS_0000 0x00000000
61#define CS_0001 0x10000000
62#define CS_0010 0x20000000
63#define CS_0011 0x30000000
64#define CS_0100 0x40000000
65#define CS_0101 0x50000000
66#define CS_0110 0x60000000
67#define CS_0111 0x70000000
68#define CS_1000 0x80000000
69#define CS_1001 0x90000000
70#define CS_1010 0xA0000000
71#define CS_1011 0xB0000000
72#define CS_1100 0xC0000000
73#define CS_1101 0xD0000000
74#define CS_1110 0xE0000000
75#define CS_1111 0xF0000000
76
77#define BS_0000 0x00000000
78#define BS_0001 0x01000000
79#define BS_0010 0x02000000
80#define BS_0011 0x03000000
81#define BS_0100 0x04000000
82#define BS_0101 0x05000000
83#define BS_0110 0x06000000
84#define BS_0111 0x07000000
85#define BS_1000 0x08000000
86#define BS_1001 0x09000000
87#define BS_1010 0x0A000000
88#define BS_1011 0x0B000000
89#define BS_1100 0x0C000000
90#define BS_1101 0x0D000000
91#define BS_1110 0x0E000000
92#define BS_1111 0x0F000000
93
94#define GPL0_AAAA 0x00000000
95#define GPL0_AAA0 0x00200000
96#define GPL0_AAA1 0x00300000
97#define GPL0_000A 0x00800000
98#define GPL0_0000 0x00A00000
99#define GPL0_0001 0x00B00000
100#define GPL0_111A 0x00C00000
101#define GPL0_1110 0x00E00000
102#define GPL0_1111 0x00F00000
103
104#define GPL1_0000 0x00000000
105#define GPL1_0001 0x00040000
106#define GPL1_1110 0x00080000
107#define GPL1_1111 0x000C0000
108
109#define GPL2_0000 0x00000000
110#define GPL2_0001 0x00010000
111#define GPL2_1110 0x00020000
112#define GPL2_1111 0x00030000
113
114#define GPL3_0000 0x00000000
115#define GPL3_0001 0x00004000
116#define GPL3_1110 0x00008000
117#define GPL3_1111 0x0000C000
118
119#define GPL4_0000 0x00000000
120#define GPL4_0001 0x00001000
121#define GPL4_1110 0x00002000
122#define GPL4_1111 0x00003000
123
124#define GPL5_0000 0x00000000
125#define GPL5_0001 0x00000400
126#define GPL5_1110 0x00000800
127#define GPL5_1111 0x00000C00
128#define LOOP 0x00000080
129
130#define EXEN 0x00000040
131
132#define AMX_COL 0x00000000
133#define AMX_ROW 0x00000020
134#define AMX_MAR 0x00000030
135
136#define NA 0x00000008
137
138#define UTA 0x00000004
139
140#define TODT 0x00000002
141
142#define LAST 0x00000001
143
144#define A10_AAAA GPL0_AAAA
145#define A10_AAA0 GPL0_AAA0
146#define A10_AAA1 GPL0_AAA1
147#define A10_000A GPL0_000A
148#define A10_0000 GPL0_0000
149#define A10_0001 GPL0_0001
150#define A10_111A GPL0_111A
151#define A10_1110 GPL0_1110
152#define A10_1111 GPL0_1111
153
154#define RAS_0000 GPL1_0000
155#define RAS_0001 GPL1_0001
156#define RAS_1110 GPL1_1110
157#define RAS_1111 GPL1_1111
158
159#define CAS_0000 GPL2_0000
160#define CAS_0001 GPL2_0001
161#define CAS_1110 GPL2_1110
162#define CAS_1111 GPL2_1111
163
164#define WE_0000 GPL3_0000
165#define WE_0001 GPL3_0001
166#define WE_1110 GPL3_1110
167#define WE_1111 GPL3_1111
168
169/* #define CAS_LATENCY 3 */
170#define CAS_LATENCY 2
171
172const uint sdram_table[0x40] = {
173
174#if CAS_LATENCY == 3
175 /* RSS */
176 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
177 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
178 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
179 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
180 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
181 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
182 _NOT_USED_, _NOT_USED_,
183
184 /* RBS */
185 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
186 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
187 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
188 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
189 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
190 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
191 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
192 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
193 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
194 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
195
196 /* WSS */
197 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
198 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
199 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
200 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
201 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
202 _NOT_USED_, _NOT_USED_, _NOT_USED_,
203
204 /* WBS */
205 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
206 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
207 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
208 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
209 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
210 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
211 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
212 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
213 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
214 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
215 _NOT_USED_, _NOT_USED_, _NOT_USED_,
216#endif
217
218#if CAS_LATENCY == 2
219 /* RSS */
220 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
221 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
222 CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
223 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
224 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
225 _NOT_USED_,
226 _NOT_USED_, _NOT_USED_,
227
228 /* RBS */
229 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
230 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
231 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
232 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
233 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
234 CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
235 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
236 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
237 _NOT_USED_,
238 _NOT_USED_, _NOT_USED_, _NOT_USED_,
239 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
240
241 /* WSS */
242 CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
243 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
244 CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
245 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
246 _NOT_USED_,
247 _NOT_USED_, _NOT_USED_,
248 _NOT_USED_,
249
250 /* WBS */
251 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
252 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
253 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
254 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
255 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
256 CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
257 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
258 _NOT_USED_,
259 _NOT_USED_, _NOT_USED_, _NOT_USED_,
260 _NOT_USED_, _NOT_USED_, _NOT_USED_,
261 _NOT_USED_, _NOT_USED_,
262
263#endif
264
265 /* UPT */
266 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
267 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
268 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
269 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
270 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
271 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
272 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
273 _NOT_USED_, _NOT_USED_,
274
275 /* EXC */
276 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
277 _NOT_USED_,
278
279 /* REG */
280 CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
281 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
282};
283
284static const uint nandcs_table[0x40] = {
285 /* RSS */
286 CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
287 CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
288 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
289 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
290 CS_0000 | GPL4_0000 | GPL5_1111,
291 CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
292 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
293 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
294
295 /* RBS */
296 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
297 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
298 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
299 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
300
301 /* WSS */
302 CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
303 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
304 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
305 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
306 CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
307 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
308 CS_0000 | GPL4_1111 | GPL5_1111,
309 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
310
311 /* WBS */
312 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
313 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
314 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
315 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
316
317 /* UPT */
318 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
319 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
320 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
321
322 /* EXC */
323 CS_0001 | LAST,
324 _NOT_USED_,
325
326 /* REG */
327 CS_1110 ,
328 CS_0001 | LAST,
329};
330
331/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
332/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
333#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
334
335/* 9 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]336#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]337 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
338 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
339
340void check_ram(unsigned int addr, unsigned int size)
341{
342 unsigned int i, j, v, vv;
343 volatile unsigned int *p;
344 unsigned int pv;
345
346 p = (unsigned int *)addr;
347 pv = (unsigned int)p;
348 for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
349 *p++ = pv;
350
351 p = (unsigned int *)addr;
352 for (i = 0; i < size / sizeof(unsigned int); i++) {
353 v = (unsigned int)p;
354 vv = *p;
355 if (vv != v) {
356 printf("%p: read %08x instead of %08x\n", p, vv, v);
357 hang();
358 }
359 p++;
360 }
361
362 for (j = 0; j < 5; j++) {
363 switch (j) {
364 case 0: v = 0x00000000; break;
365 case 1: v = 0xffffffff; break;
366 case 2: v = 0x55555555; break;
367 case 3: v = 0xaaaaaaaa; break;
368 default:v = 0xdeadbeef; break;
369 }
370 p = (unsigned int *)addr;
371 for (i = 0; i < size / sizeof(unsigned int); i++) {
372 *p = v;
373 vv = *p;
374 if (vv != v) {
375 printf("%p: read %08x instead of %08x\n", p, vv, v);
376 hang();
377 }
378 *p = ~v;
379 p++;
380 }
381 }
382}
383
384#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
385
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]386phys_size_t initdram(int board_type)
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]387{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]388 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]389 volatile memctl8xx_t *memctl = &immap->im_memctl;
390 long int size;
391 u32 d1, d2;
392
393 upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
394
395 /*
396 * Preliminary prescaler for refresh
397 */
398 memctl->memc_mptpr = MPTPR_PTP_DIV8;
399
400 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
401
402 /*
403 * Map controller bank 3 to the SDRAM bank at preliminary address.
404 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]405 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
406 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]407
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]408 memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]409
410 udelay(200);
411
412 /* perform SDRAM initialisation sequence */
413 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
414 udelay(1);
415
416 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
417 udelay(1);
418
419 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
420 udelay(1);
421
422 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
423
424 udelay(10000);
425
426
427 d1 = 0xAA55AA55;
428 *(volatile u32 *)0 = d1;
429 d2 = *(volatile u32 *)0;
430 if (d1 != d2) {
431 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
432 DO_LOOP;
433 }
434
435 d1 = 0x55AA55AA;
436 *(volatile u32 *)0 = d1;
437 d2 = *(volatile u32 *)0;
438 if (d1 != d2) {
439 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
440 DO_LOOP;
441 }
442
443 d1 = 0x12345678;
444 *(volatile u32 *)0 = d1;
445 d2 = *(volatile u32 *)0;
446 if (d1 != d2) {
447 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
448 DO_LOOP;
449 }
450
451 size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
452
453 return size;
454}
455
456/* ------------------------------------------------------------------------- */
457
458void reset_phys(void)
459{
460 int phyno;
461 unsigned short v;
462
463 udelay(10000);
464 /* reset the damn phys */
465 mii_init();
466
467 for (phyno = 0; phyno < 32; ++phyno) {
Mike Frysingerd63ee712010-12-23 15:40:12 -0500[diff] [blame]468 miiphy_read("FEC", phyno, MII_PHYSID1, &v);
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]469 if (v == 0xFFFF)
470 continue;
Mike Frysingerd63ee712010-12-23 15:40:12 -0500[diff] [blame]471 miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN);
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]472 udelay(10000);
Mike Frysingerd63ee712010-12-23 15:40:12 -0500[diff] [blame]473 miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]474 udelay(10000);
475 }
476}
477
478/* ------------------------------------------------------------------------- */
479
480/* GP = general purpose, SP = special purpose (on chip peripheral) */
481
482/* bits that can have a special purpose or can be configured as inputs/outputs */
483#define PA_GP_INMASK _BW(6)
484#define PA_GP_OUTMASK (_BW(7))
485#define PA_SP_MASK 0
486#define PA_ODR_VAL 0
487#define PA_GP_OUTVAL (_BW(7))
488#define PA_SP_DIRVAL 0
489
490#define PB_GP_INMASK 0
491#define PB_GP_OUTMASK (_B(23))
492#define PB_SP_MASK 0
493#define PB_ODR_VAL 0
494#define PB_GP_OUTVAL (_B(23))
495#define PB_SP_DIRVAL 0
496
497#define PC_GP_INMASK 0
498#define PC_GP_OUTMASK (_BW(15))
499
500#define PC_SP_MASK 0
501#define PC_SOVAL 0
502#define PC_INTVAL 0
503#define PC_GP_OUTVAL 0
504#define PC_SP_DIRVAL 0
505
506#define PE_GP_INMASK 0
507#define PE_GP_OUTMASK 0
508#define PE_GP_OUTVAL 0
509
510#define PE_SP_MASK 0
511#define PE_ODR_VAL 0
512#define PE_SP_DIRVAL 0
513
514int board_early_init_f(void)
515{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]516 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]517 volatile iop8xx_t *ioport = &immap->im_ioport;
518 volatile cpm8xx_t *cpm = &immap->im_cpm;
519 volatile memctl8xx_t *memctl = &immap->im_memctl;
520
521 (void)ioport;
522 (void)cpm;
523#if 1
524 /* NAND chip select */
525 upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
526 memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
527 memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
528 memctl->memc_mbmr = 0; /* all clear */
529#endif
530
531 memctl->memc_br5 &= ~BR_V;
532 memctl->memc_br6 &= ~BR_V;
533 memctl->memc_br7 &= ~BR_V;
534
535#if 1
536 ioport->iop_padat = PA_GP_OUTVAL;
537 ioport->iop_paodr = PA_ODR_VAL;
538 ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
539 ioport->iop_papar = PA_SP_MASK;
540
541 cpm->cp_pbdat = PB_GP_OUTVAL;
542 cpm->cp_pbodr = PB_ODR_VAL;
543 cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
544 cpm->cp_pbpar = PB_SP_MASK;
545
546 ioport->iop_pcdat = PC_GP_OUTVAL;
547 ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
548 ioport->iop_pcso = PC_SOVAL;
549 ioport->iop_pcint = PC_INTVAL;
550 ioport->iop_pcpar = PC_SP_MASK;
551
552 cpm->cp_pedat = PE_GP_OUTVAL;
553 cpm->cp_peodr = PE_ODR_VAL;
554 cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
555 cpm->cp_pepar = PE_SP_MASK;
556#endif
557
558 return 0;
559}
560
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]561#ifdef CONFIG_HW_WATCHDOG
562
563void hw_watchdog_reset(void)
564{
565 /* XXX add here the really funky stuff */
566}
567
568#endif
569
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]570#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]571int overwrite_console(void)
572{
573 /* printf("overwrite_console called\n"); */
574 return 0;
575}
576#endif
577
578extern int drv_phone_init(void);
579extern int drv_phone_use_me(void);
580extern int drv_phone_is_idle(void);
581
582int misc_init_r(void)
583{
584 return 0;
585}
586
587int last_stage_init(void)
588{
589 reset_phys();
590
591 return 0;
592}