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git01.mediatek.com / filogic / uboot / a9e1762a98b557b6db5f86e297f436fda1fc8158 / . / arch / arm / dts / k3-am62a7-sk-u-boot.dtsi
blob: 7dfbeb10c323bbe1f935a50e3efc87b3276f044e [file] [log] [blame]
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common AM62A EVM dts file for SPLs
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]7#include "k3-am62a-sk-binman.dtsi"
8
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]9/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]12 };
13
14 memory@80000000 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]15 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]16 };
17};
18
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]19&cbass_main {
20 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]21};
22
23&dmss {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]24 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]25};
26
27&secure_proxy_main {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]28 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]29};
30
31&dmsc {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]32 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]33};
34
35&k3_pds {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]36 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]37};
38
39&k3_clks {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]40 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]41};
42
43&k3_reset {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]44 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]45};
46
47&wkup_conf {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]48 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]49};
50
51&chipid {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]52 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]53};
54
55&main_pmx0 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]56 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]57};
58
59&main_uart0 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]60 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]61};
62
63&main_uart0_pins_default {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]64 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]65};
66
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]67&cbass_mcu {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]68 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]69};
70
71&cbass_wakeup {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]72 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]73};
74
75&mcu_pmx0 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]76 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]77};
78
79&main_gpio0 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]80 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]81};
82
83&main_i2c0 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]84 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]85};
86
87&main_i2c0_pins_default {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]88 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]89};
90
91&main_i2c1 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]92 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]93};
94
95&main_i2c1_pins_default {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]96 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]97};
98
99&exp1 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]100 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]101};
102
103&sdhci1 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]104 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]105};
106
107&main_mmc1_pins_default {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]108 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]109};
110
111&k3_reset {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]112 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]113};
114
115&dmsc {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]116 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]117};
118
119&vdd_mmc1 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]120 bootph-all;
121};
122
123&main_bcdma {
124 reg = <0x00 0x485c0100 0x00 0x100>,
125 <0x00 0x4c000000 0x00 0x20000>,
126 <0x00 0x4a820000 0x00 0x20000>,
127 <0x00 0x4aa40000 0x00 0x20000>,
128 <0x00 0x4bc00000 0x00 0x100000>,
129 <0x00 0x48600000 0x00 0x8000>,
130 <0x00 0x484a4000 0x00 0x2000>,
131 <0x00 0x484c2000 0x00 0x2000>;
132 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
133 "ringrt" , "cfg", "tchan", "rchan";
134 bootph-all;
135};
136
137&main_pktdma {
138 reg = <0x00 0x485c0000 0x00 0x100>,
139 <0x00 0x4a800000 0x00 0x20000>,
140 <0x00 0x4aa00000 0x00 0x20000>,
141 <0x00 0x4b800000 0x00 0x200000>,
142 <0x00 0x485e0000 0x00 0x10000>,
143 <0x00 0x484a0000 0x00 0x2000>,
144 <0x00 0x484c0000 0x00 0x2000>,
145 <0x00 0x48430000 0x00 0x1000>;
146 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
147 "cfg", "tchan", "rchan", "rflow";
148 bootph-all;
149};
150
151&main_mdio1_pins_default {
152 bootph-all;
153};
154
155&cpsw3g_mdio {
156 bootph-all;
157};
158
159&cpsw3g_phy0 {
160 bootph-all;
161};
162
163&main_rgmii1_pins_default {
164 bootph-all;
165};
166
167&phy_gmii_sel {
168 bootph-all;
169};
170
171&cpsw3g {
172 bootph-all;
173 ethernet-ports {
174 bootph-all;
175 };
176};
177
178&cpsw_port1 {
179 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]180};