| Jon Smirl | bc03df9 | 2009-06-14 18:21:28 -0400 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2004 |
| 3 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
| 4 | * |
| 5 | * Eric Schumann, Phytec Messtechnik |
| 6 | * adapted for mt46v32m16-75 DDR-RAM |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | #define SDRAM_DDR 1 /* is DDR */ |
| 28 | |
| 29 | /* Settings for XLB = 132 MHz */ |
| 30 | |
| 31 | #define SDRAM_MODE 0x018D0000 |
| 32 | #define SDRAM_EMODE 0x40090000 |
| 33 | #define SDRAM_CONTROL 0x71500F00 |
| 34 | #define SDRAM_CONFIG1 0x73711930 |
| 35 | #define SDRAM_CONFIG2 0x47770000 |
| 36 | |
| 37 | #define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */ |