Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
Stelian Pop | 5ee0c7f | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * |
| 7 | * Configuation settings for the AT91SAM9263EK board. |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
Xu, Hong | 504e4e1 | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 13 | /* |
| 14 | * SoC must be defined first, before hardware.h is included. |
| 15 | * In this case SoC is defined in boards.cfg. |
| 16 | */ |
| 17 | #include <asm/hardware.h> |
| 18 | |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 19 | /* ARM asynchronous clock */ |
Xu, Hong | 504e4e1 | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 20 | #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ |
| 21 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 22 | |
Jean-Christophe PLAGNIOL-VILLARD | 23164f1 | 2009-04-16 21:30:44 +0200 | [diff] [blame] | 23 | #define CONFIG_ARCH_CPU_INIT |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 24 | |
| 25 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 26 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
| 27 | #define CONFIG_INITRD_TAG 1 |
| 28 | |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 29 | #ifndef CONFIG_SYS_USE_BOOT_NORFLASH |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 30 | #define CONFIG_SKIP_LOWLEVEL_INIT |
Xu, Hong | 504e4e1 | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 31 | #else |
| 32 | #define CONFIG_SYS_USE_NORFLASH |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 33 | #endif |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 34 | |
| 35 | /* |
| 36 | * Hardware drivers |
| 37 | */ |
Xu, Hong | 504e4e1 | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 38 | #define CONFIG_ATMEL_LEGACY |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 39 | |
Stelian Pop | e068a9b | 2008-05-08 14:52:31 +0200 | [diff] [blame] | 40 | /* LCD */ |
Stelian Pop | e068a9b | 2008-05-08 14:52:31 +0200 | [diff] [blame] | 41 | #define LCD_BPP LCD_COLOR8 |
| 42 | #define CONFIG_LCD_LOGO 1 |
| 43 | #undef LCD_TEST_PATTERN |
| 44 | #define CONFIG_LCD_INFO 1 |
| 45 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 |
Stelian Pop | e068a9b | 2008-05-08 14:52:31 +0200 | [diff] [blame] | 46 | #define CONFIG_ATMEL_LCD 1 |
| 47 | #define CONFIG_ATMEL_LCD_BGR555 1 |
Stelian Pop | e068a9b | 2008-05-08 14:52:31 +0200 | [diff] [blame] | 48 | |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 49 | /* |
| 50 | * BOOTP options |
| 51 | */ |
| 52 | #define CONFIG_BOOTP_BOOTFILESIZE 1 |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 53 | |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 54 | /* SDRAM */ |
Xu, Hong | 504e4e1 | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 55 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 56 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 |
| 57 | |
| 58 | #define CONFIG_SYS_INIT_SP_ADDR \ |
Wenyou Yang | a4952c1 | 2017-04-18 15:31:00 +0800 | [diff] [blame] | 59 | (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 60 | |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 61 | /* NOR flash, if populated */ |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 62 | #ifdef CONFIG_SYS_USE_NORFLASH |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 63 | #define PHYS_FLASH_1 0x10000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 64 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
| 65 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 66 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 67 | |
| 68 | #define CONFIG_SYS_MONITOR_SEC 1:0-3 |
| 69 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 70 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) |
esw@bus-elektronik.de | 2aa9338 | 2012-03-19 05:18:17 +0000 | [diff] [blame] | 71 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 72 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) |
| 73 | |
| 74 | /* Address and size of Primary Environment Sector */ |
esw@bus-elektronik.de | 2aa9338 | 2012-03-19 05:18:17 +0000 | [diff] [blame] | 75 | #define CONFIG_ENV_SIZE 0x10000 |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 76 | |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 77 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Marek Vasut | fd5ba89 | 2012-09-23 17:41:23 +0200 | [diff] [blame] | 78 | "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 79 | "update=" \ |
| 80 | "protect off ${monitor_base} +${filesize};" \ |
| 81 | "erase ${monitor_base} +${filesize};" \ |
Andreas Bießmann | 46a8ab7 | 2012-06-28 02:32:32 +0000 | [diff] [blame] | 82 | "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 83 | "protect on ${monitor_base} +${filesize}\0" |
| 84 | |
| 85 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 86 | #define MASTER_PLL_MUL 171 |
| 87 | #define MASTER_PLL_DIV 14 |
Jens Scharsig | c3c10ea | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 88 | #define MASTER_PLL_OUT 3 |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 89 | |
| 90 | /* clocks */ |
| 91 | #define CONFIG_SYS_MOR_VAL \ |
Jens Scharsig | c3c10ea | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 92 | (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) |
| 93 | #define CONFIG_SYS_PLLAR_VAL \ |
| 94 | (AT91_PMC_PLLAR_29 | \ |
| 95 | AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ |
| 96 | AT91_PMC_PLLXR_PLLCOUNT(63) | \ |
| 97 | AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ |
| 98 | AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 99 | |
| 100 | /* PCK/2 = MCK Master Clock from PLLA */ |
| 101 | #define CONFIG_SYS_MCKR1_VAL \ |
Jens Scharsig | c3c10ea | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 102 | (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ |
| 103 | AT91_PMC_MCKR_MDIV_2) |
| 104 | |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 105 | /* PCK/2 = MCK Master Clock from PLLA */ |
| 106 | #define CONFIG_SYS_MCKR2_VAL \ |
Jens Scharsig | c3c10ea | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 107 | (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ |
| 108 | AT91_PMC_MCKR_MDIV_2) |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 109 | |
| 110 | /* define PDC[31:16] as DATA[31:16] */ |
| 111 | #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 |
| 112 | /* no pull-up for D[31:16] */ |
| 113 | #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 |
| 114 | /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ |
Jens Scharsig | c3c10ea | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 115 | #define CONFIG_SYS_MATRIX_EBICSA_VAL \ |
| 116 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ |
| 117 | AT91_MATRIX_CSA_EBI_CS1A) |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 118 | |
| 119 | /* SDRAM */ |
| 120 | /* SDRAMC_MR Mode register */ |
| 121 | #define CONFIG_SYS_SDRC_MR_VAL1 0 |
| 122 | /* SDRAMC_TR - Refresh Timer register */ |
| 123 | #define CONFIG_SYS_SDRC_TR_VAL1 0x13C |
| 124 | /* SDRAMC_CR - Configuration register*/ |
| 125 | #define CONFIG_SYS_SDRC_CR_VAL \ |
| 126 | (AT91_SDRAMC_NC_9 | \ |
| 127 | AT91_SDRAMC_NR_13 | \ |
| 128 | AT91_SDRAMC_NB_4 | \ |
| 129 | AT91_SDRAMC_CAS_3 | \ |
| 130 | AT91_SDRAMC_DBW_32 | \ |
| 131 | (1 << 8) | /* Write Recovery Delay */ \ |
| 132 | (7 << 12) | /* Row Cycle Delay */ \ |
| 133 | (2 << 16) | /* Row Precharge Delay */ \ |
| 134 | (2 << 20) | /* Row to Column Delay */ \ |
| 135 | (5 << 24) | /* Active to Precharge Delay */ \ |
| 136 | (1 << 28)) /* Exit Self Refresh to Active Delay */ |
| 137 | |
| 138 | /* Memory Device Register -> SDRAM */ |
| 139 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM |
| 140 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE |
| 141 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ |
| 142 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH |
| 143 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ |
| 144 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ |
| 145 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ |
| 146 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ |
| 147 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ |
| 148 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ |
| 149 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ |
| 150 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ |
| 151 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR |
| 152 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ |
| 153 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL |
| 154 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ |
| 155 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ |
| 156 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ |
| 157 | |
| 158 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ |
Jens Scharsig | c3c10ea | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 159 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ |
| 160 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ |
| 161 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) |
| 162 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
| 163 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ |
| 164 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 165 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
Jens Scharsig | c3c10ea | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 166 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 167 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
Jens Scharsig | c3c10ea | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 168 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
| 169 | AT91_SMC_MODE_DBW_16 | \ |
| 170 | AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 171 | |
| 172 | /* user reset enable */ |
| 173 | #define CONFIG_SYS_RSTC_RMR_VAL \ |
| 174 | (AT91_RSTC_KEY | \ |
Jens Scharsig | c3c10ea | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 175 | AT91_RSTC_MR_URSTEN | \ |
| 176 | AT91_RSTC_MR_ERSTL(15)) |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 177 | |
| 178 | /* Disable Watchdog */ |
| 179 | #define CONFIG_SYS_WDTC_WDMR_VAL \ |
Jens Scharsig | c3c10ea | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 180 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
| 181 | AT91_WDT_MR_WDV(0xfff) | \ |
| 182 | AT91_WDT_MR_WDDIS | \ |
| 183 | AT91_WDT_MR_WDD(0xfff)) |
| 184 | |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 185 | #endif |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 186 | #endif |
| 187 | |
| 188 | /* NAND flash */ |
Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 189 | #ifdef CONFIG_CMD_NAND |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Xu, Hong | 504e4e1 | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 191 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | #define CONFIG_SYS_NAND_DBW_8 1 |
Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 193 | /* our ALE is AD21 */ |
| 194 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 195 | /* our CLE is AD22 */ |
| 196 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
Xu, Hong | 504e4e1 | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 197 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 |
| 198 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 |
Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 199 | #endif |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 200 | |
| 201 | /* Ethernet */ |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 202 | #define CONFIG_RESET_PHY_R 1 |
Heiko Schocher | 8a84ae1 | 2013-11-18 08:07:23 +0100 | [diff] [blame] | 203 | #define CONFIG_AT91_WANTS_COMMON_PHY |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 204 | |
| 205 | /* USB */ |
Jean-Christophe PLAGNIOL-VILLARD | d42643f | 2009-03-27 23:26:44 +0100 | [diff] [blame] | 206 | #define CONFIG_USB_ATMEL |
Bo Shen | 4a985df | 2013-10-21 16:14:00 +0800 | [diff] [blame] | 207 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 208 | #define CONFIG_USB_OHCI_NEW 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
| 210 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ |
| 211 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" |
| 212 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 213 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 214 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 215 | |
Xu, Hong | 504e4e1 | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 216 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 217 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 218 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 219 | #ifdef CONFIG_SYS_USE_DATAFLASH |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 220 | |
| 221 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ |
Wenyou.Yang@microchip.com | 67d4cad | 2017-07-21 13:40:09 +0800 | [diff] [blame] | 222 | #define CONFIG_ENV_OFFSET 0x4200 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 223 | #define CONFIG_ENV_SIZE 0x4200 |
Wenyou.Yang@microchip.com | 67d4cad | 2017-07-21 13:40:09 +0800 | [diff] [blame] | 224 | #define CONFIG_ENV_SECT_SIZE 0x210 |
Wenyou.Yang@microchip.com | 67d4cad | 2017-07-21 13:40:09 +0800 | [diff] [blame] | 225 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ |
| 226 | "sf read 0x22000000 0x84000 0x294000; " \ |
| 227 | "bootm 0x22000000" |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 228 | |
Jean-Christophe PLAGNIOL-VILLARD | 3277473 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 229 | #elif CONFIG_SYS_USE_NANDFLASH |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 230 | |
| 231 | /* bootstrap + u-boot + env + linux in nandflash */ |
Nicolas Ferre | 6492244 | 2018-05-09 10:30:25 +0300 | [diff] [blame] | 232 | #define CONFIG_ENV_OFFSET 0x140000 |
Bo Shen | a8fd063 | 2013-02-20 00:16:25 +0000 | [diff] [blame] | 233 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 234 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
Bo Shen | a8fd063 | 2013-02-20 00:16:25 +0000 | [diff] [blame] | 235 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 236 | #endif |
| 237 | |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 238 | /* |
| 239 | * Size of malloc() pool |
| 240 | */ |
Xu, Hong | 504e4e1 | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 241 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 242 | |
Stelian Pop | 69c925f | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 243 | #endif |