blob: e69f66226da3c116f9b367ec664484387ddbfa47 [file] [log] [blame]
Simon Schwarz4f62e982011-09-14 15:30:16 -04001/*
2 * (C) Copyright 2006-2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Simon Schwarz4f62e982011-09-14 15:30:16 -04006 */
7
8#include <common.h>
9#include <nand.h>
10#include <asm/io.h>
Ilya Yanok4e699622011-11-28 06:37:37 +000011#include <linux/mtd/nand_ecc.h>
Simon Schwarz4f62e982011-09-14 15:30:16 -040012
13static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
14static nand_info_t mtd;
15static struct nand_chip nand_chip;
16
Stefano Babic533607c2011-12-15 10:55:37 +010017#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
18 CONFIG_SYS_NAND_ECCSIZE)
19#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
20
21
Simon Schwarz4f62e982011-09-14 15:30:16 -040022#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
23/*
24 * NAND command for small page NAND devices (512)
25 */
26static int nand_command(int block, int page, uint32_t offs,
27 u8 cmd)
28{
29 struct nand_chip *this = mtd.priv;
30 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
31
32 while (!this->dev_ready(&mtd))
33 ;
34
35 /* Begin command latch cycle */
36 this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
37 /* Set ALE and clear CLE to start address cycle */
38 /* Column address */
39 this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
40 this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
41 this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
42 NAND_CTRL_ALE); /* A[24:17] */
43#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
44 /* One more address cycle for devices > 32MiB */
45 this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
46 NAND_CTRL_ALE); /* A[28:25] */
47#endif
48 /* Latch in address */
49 this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
50
51 /*
52 * Wait a while for the data to be ready
53 */
54 while (!this->dev_ready(&mtd))
55 ;
56
57 return 0;
58}
59#else
60/*
61 * NAND command for large page NAND devices (2k)
62 */
63static int nand_command(int block, int page, uint32_t offs,
64 u8 cmd)
65{
66 struct nand_chip *this = mtd.priv;
67 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
68 void (*hwctrl)(struct mtd_info *mtd, int cmd,
69 unsigned int ctrl) = this->cmd_ctrl;
70
71 while (!this->dev_ready(&mtd))
72 ;
73
74 /* Emulate NAND_CMD_READOOB */
75 if (cmd == NAND_CMD_READOOB) {
76 offs += CONFIG_SYS_NAND_PAGE_SIZE;
77 cmd = NAND_CMD_READ0;
78 }
79
80 /* Shift the offset from byte addressing to word addressing. */
Brian Norris67675222014-05-06 00:46:17 +053081 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
Simon Schwarz4f62e982011-09-14 15:30:16 -040082 offs >>= 1;
83
84 /* Begin command latch cycle */
85 hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
86 /* Set ALE and clear CLE to start address cycle */
87 /* Column address */
88 hwctrl(&mtd, offs & 0xff,
89 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
90 hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
91 /* Row address */
92 hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
93 hwctrl(&mtd, ((page_addr >> 8) & 0xff),
94 NAND_CTRL_ALE); /* A[27:20] */
95#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
96 /* One more address cycle for devices > 128MiB */
97 hwctrl(&mtd, (page_addr >> 16) & 0x0f,
98 NAND_CTRL_ALE); /* A[31:28] */
99#endif
100 /* Latch in address */
101 hwctrl(&mtd, NAND_CMD_READSTART,
102 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
103 hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
104
105 /*
106 * Wait a while for the data to be ready
107 */
108 while (!this->dev_ready(&mtd))
109 ;
110
111 return 0;
112}
113#endif
114
115static int nand_is_bad_block(int block)
116{
117 struct nand_chip *this = mtd.priv;
Vladimir Zapolskiycb8183d2015-07-18 01:47:08 +0300118 u_char bb_data[2];
Simon Schwarz4f62e982011-09-14 15:30:16 -0400119
120 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
121 NAND_CMD_READOOB);
122
123 /*
124 * Read one byte (or two if it's a 16 bit chip).
125 */
126 if (this->options & NAND_BUSWIDTH_16) {
Vladimir Zapolskiycb8183d2015-07-18 01:47:08 +0300127 this->read_buf(&mtd, bb_data, 2);
128 if (bb_data[0] != 0xff || bb_data[1] != 0xff)
Simon Schwarz4f62e982011-09-14 15:30:16 -0400129 return 1;
130 } else {
Vladimir Zapolskiycb8183d2015-07-18 01:47:08 +0300131 this->read_buf(&mtd, bb_data, 1);
132 if (bb_data[0] != 0xff)
Simon Schwarz4f62e982011-09-14 15:30:16 -0400133 return 1;
134 }
135
136 return 0;
137}
138
Heiko Schocher44bd9b32011-11-01 20:00:30 +0000139#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
140static int nand_read_page(int block, int page, uchar *dst)
141{
142 struct nand_chip *this = mtd.priv;
Stefano Babic533607c2011-12-15 10:55:37 +0100143 u_char ecc_calc[ECCTOTAL];
144 u_char ecc_code[ECCTOTAL];
145 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
Heiko Schocher44bd9b32011-11-01 20:00:30 +0000146 int i;
147 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
148 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
Stefano Babic533607c2011-12-15 10:55:37 +0100149 int eccsteps = ECCSTEPS;
Heiko Schocher44bd9b32011-11-01 20:00:30 +0000150 uint8_t *p = dst;
Heiko Schocher44bd9b32011-11-01 20:00:30 +0000151
Heiko Schocher44bd9b32011-11-01 20:00:30 +0000152 nand_command(block, page, 0, NAND_CMD_READOOB);
153 this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
154 nand_command(block, page, 0, NAND_CMD_READ0);
155
156 /* Pick the ECC bytes out of the oob data */
Stefano Babic533607c2011-12-15 10:55:37 +0100157 for (i = 0; i < ECCTOTAL; i++)
Heiko Schocher44bd9b32011-11-01 20:00:30 +0000158 ecc_code[i] = oob_data[nand_ecc_pos[i]];
159
160
161 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
162 this->ecc.hwctl(&mtd, NAND_ECC_READ);
163 this->read_buf(&mtd, p, eccsize);
164 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
Anatolij Gustschinf552e7a2011-12-03 06:46:08 +0000165 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
Heiko Schocher44bd9b32011-11-01 20:00:30 +0000166 }
167
168 return 0;
169}
170#else
Simon Schwarz4f62e982011-09-14 15:30:16 -0400171static int nand_read_page(int block, int page, void *dst)
172{
173 struct nand_chip *this = mtd.priv;
Stefano Babic533607c2011-12-15 10:55:37 +0100174 u_char ecc_calc[ECCTOTAL];
175 u_char ecc_code[ECCTOTAL];
176 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
Simon Schwarz4f62e982011-09-14 15:30:16 -0400177 int i;
178 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
179 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
Stefano Babic533607c2011-12-15 10:55:37 +0100180 int eccsteps = ECCSTEPS;
Simon Schwarz4f62e982011-09-14 15:30:16 -0400181 uint8_t *p = dst;
Simon Schwarz4f62e982011-09-14 15:30:16 -0400182
183 nand_command(block, page, 0, NAND_CMD_READ0);
184
Simon Schwarz4f62e982011-09-14 15:30:16 -0400185 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
Ilya Yanok4e699622011-11-28 06:37:37 +0000186 if (this->ecc.mode != NAND_ECC_SOFT)
187 this->ecc.hwctl(&mtd, NAND_ECC_READ);
Simon Schwarz4f62e982011-09-14 15:30:16 -0400188 this->read_buf(&mtd, p, eccsize);
189 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
190 }
191 this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
192
193 /* Pick the ECC bytes out of the oob data */
Stefano Babic533607c2011-12-15 10:55:37 +0100194 for (i = 0; i < ECCTOTAL; i++)
Simon Schwarz4f62e982011-09-14 15:30:16 -0400195 ecc_code[i] = oob_data[nand_ecc_pos[i]];
196
Stefano Babic533607c2011-12-15 10:55:37 +0100197 eccsteps = ECCSTEPS;
Simon Schwarz4f62e982011-09-14 15:30:16 -0400198 p = dst;
199
200 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
201 /* No chance to do something with the possible error message
202 * from correct_data(). We just hope that all possible errors
203 * are corrected by this routine.
204 */
Anatolij Gustschinf552e7a2011-12-03 06:46:08 +0000205 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
Simon Schwarz4f62e982011-09-14 15:30:16 -0400206 }
207
208 return 0;
209}
Heiko Schocher44bd9b32011-11-01 20:00:30 +0000210#endif
Simon Schwarz4f62e982011-09-14 15:30:16 -0400211
212int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
213{
214 unsigned int block, lastblock;
215 unsigned int page;
216
217 /*
218 * offs has to be aligned to a page address!
219 */
220 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
221 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
222 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
223
224 while (block <= lastblock) {
225 if (!nand_is_bad_block(block)) {
226 /*
227 * Skip bad blocks
228 */
229 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
230 nand_read_page(block, page, dst);
231 dst += CONFIG_SYS_NAND_PAGE_SIZE;
232 page++;
233 }
234
235 page = 0;
236 } else {
237 lastblock++;
238 }
239
240 block++;
241 }
242
243 return 0;
244}
245
246/* nand_init() - initialize data to make nand usable by SPL */
247void nand_init(void)
248{
249 /*
250 * Init board specific nand support
251 */
252 mtd.priv = &nand_chip;
253 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
254 (void __iomem *)CONFIG_SYS_NAND_BASE;
Simon Schwarz4f62e982011-09-14 15:30:16 -0400255 board_nand_init(&nand_chip);
256
Ilya Yanok4e699622011-11-28 06:37:37 +0000257#ifdef CONFIG_SPL_NAND_SOFTECC
258 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
259 nand_chip.ecc.calculate = nand_calculate_ecc;
260 nand_chip.ecc.correct = nand_correct_data;
261 }
262#endif
263
Simon Schwarz4f62e982011-09-14 15:30:16 -0400264 if (nand_chip.select_chip)
265 nand_chip.select_chip(&mtd, 0);
266}
267
268/* Unselect after operation */
269void nand_deselect(void)
270{
271 if (nand_chip.select_chip)
272 nand_chip.select_chip(&mtd, -1);
273}