| Rui Miguel Silva | ee0fec7 | 2022-05-11 10:55:41 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * (C) Copyright 2022 ARM Limited |
| 4 | * (C) Copyright 2022 Linaro |
| 5 | * Rui Miguel Silva <rui.silva@linaro.org> |
| 6 | * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
| 7 | * |
| 8 | * Configuration for Corstone1000. Parts were derived from other ARM |
| 9 | * configurations. |
| 10 | */ |
| 11 | |
| 12 | #ifndef __CORSTONE1000_H |
| 13 | #define __CORSTONE1000_H |
| 14 | |
| 15 | #include <linux/sizes.h> |
| 16 | |
| 17 | #define V2M_BASE 0x80000000 |
| 18 | |
| 19 | #define CONFIG_PL011_CLOCK 50000000 |
| 20 | |
| 21 | /* Physical Memory Map */ |
| 22 | #define PHYS_SDRAM_1 (V2M_BASE) |
| 23 | #define PHYS_SDRAM_1_SIZE 0x80000000 |
| 24 | |
| 25 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 26 | |
| Rui Miguel Silva | ee0fec7 | 2022-05-11 10:55:41 +0100 | [diff] [blame] | 27 | #endif |