blob: db30812b176f9e36529452e260b847241f97fdab [file] [log] [blame]
Neil Armstrongac4fa422024-12-30 11:30:58 +01001/* SPDX-License-Identifier: GPL-2.0+ */
2#ifndef __UFSHCI_H
3#define __UFSHCI_H
4
5enum {
6 TASK_REQ_UPIU_SIZE_DWORDS = 8,
7 TASK_RSP_UPIU_SIZE_DWORDS = 8,
8 ALIGNED_UPIU_SIZE = 512,
9};
10
11/* To accommodate UFS2.0 required Command type */
12enum {
13 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
14};
15
16enum {
17 UTP_SCSI_COMMAND = 0x00000000,
18 UTP_NATIVE_UFS_COMMAND = 0x10000000,
19 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
20 UTP_REQ_DESC_INT_CMD = 0x01000000,
21};
22
23/* UTP Transfer Request Data Direction (DD) */
24enum {
25 UTP_NO_DATA_TRANSFER = 0x00000000,
26 UTP_HOST_TO_DEVICE = 0x02000000,
27 UTP_DEVICE_TO_HOST = 0x04000000,
28};
29
30/* Overall command status values */
31enum {
32 OCS_SUCCESS = 0x0,
33 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
34 OCS_INVALID_PRDT_ATTR = 0x2,
35 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
36 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
37 OCS_PEER_COMM_FAILURE = 0x5,
38 OCS_ABORTED = 0x6,
39 OCS_FATAL_ERROR = 0x7,
40 OCS_INVALID_COMMAND_STATUS = 0x0F,
41 MASK_OCS = 0x0F,
42};
43
44/* The maximum length of the data byte count field in the PRDT is 256KB */
45#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
46/* The granularity of the data byte count field in the PRDT is 32-bit */
47#define PRDT_DATA_BYTE_COUNT_PAD 4
48
49/* Controller UFSHCI version */
50enum {
51 UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
52 UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
53 UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
54 UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
55 UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
56 UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
57 UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
58};
59
60/* UFSHCI Registers */
61enum {
62 REG_CONTROLLER_CAPABILITIES = 0x00,
63 REG_UFS_VERSION = 0x08,
64 REG_CONTROLLER_DEV_ID = 0x10,
65 REG_CONTROLLER_PROD_ID = 0x14,
66 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
67 REG_INTERRUPT_STATUS = 0x20,
68 REG_INTERRUPT_ENABLE = 0x24,
69 REG_CONTROLLER_STATUS = 0x30,
70 REG_CONTROLLER_ENABLE = 0x34,
71 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
72 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
73 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
74 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
75 REG_UIC_ERROR_CODE_DME = 0x48,
76 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
77 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
78 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
79 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
80 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
81 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
82 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
83 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
84 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
85 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
86 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
87 REG_UIC_COMMAND = 0x90,
88 REG_UIC_COMMAND_ARG_1 = 0x94,
89 REG_UIC_COMMAND_ARG_2 = 0x98,
90 REG_UIC_COMMAND_ARG_3 = 0x9C,
91
92 UFSHCI_REG_SPACE_SIZE = 0xA0,
93
94 REG_UFS_CCAP = 0x100,
95 REG_UFS_CRYPTOCAP = 0x104,
96
97 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
98};
99
100/* Controller capability masks */
101enum {
102 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
103 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
104 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
105 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
106 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
107 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
108};
109
110/* Interrupt Status 20h */
111#define UTP_TRANSFER_REQ_COMPL 0x1
112#define UIC_DME_END_PT_RESET 0x2
113#define UIC_ERROR 0x4
114#define UIC_TEST_MODE 0x8
115#define UIC_POWER_MODE 0x10
116#define UIC_HIBERNATE_EXIT 0x20
117#define UIC_HIBERNATE_ENTER 0x40
118#define UIC_LINK_LOST 0x80
119#define UIC_LINK_STARTUP 0x100
120#define UTP_TASK_REQ_COMPL 0x200
121#define UIC_COMMAND_COMPL 0x400
122#define DEVICE_FATAL_ERROR 0x800
123#define CONTROLLER_FATAL_ERROR 0x10000
124#define SYSTEM_BUS_FATAL_ERROR 0x20000
125
126#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
127 UIC_HIBERNATE_EXIT |\
128 UIC_POWER_MODE)
129
130#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE)
131
132#define UFSHCD_ERROR_MASK (UIC_ERROR |\
133 DEVICE_FATAL_ERROR |\
134 CONTROLLER_FATAL_ERROR |\
135 SYSTEM_BUS_FATAL_ERROR)
136
137#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
138 CONTROLLER_FATAL_ERROR |\
139 SYSTEM_BUS_FATAL_ERROR)
140
141/* Host Controller Enable 0x34h */
142#define CONTROLLER_ENABLE 0x1
143#define CONTROLLER_DISABLE 0x0
144/* HCS - Host Controller Status 30h */
145#define DEVICE_PRESENT 0x1
146#define UTP_TRANSFER_REQ_LIST_READY 0x2
147#define UTP_TASK_REQ_LIST_READY 0x4
148#define UIC_COMMAND_READY 0x8
149#define HOST_ERROR_INDICATOR 0x10
150#define DEVICE_ERROR_INDICATOR 0x20
151#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
152
153#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
154 UTP_TASK_REQ_LIST_READY |\
155 UIC_COMMAND_READY)
156
157enum {
158 PWR_OK = 0x0,
159 PWR_LOCAL = 0x01,
160 PWR_REMOTE = 0x02,
161 PWR_BUSY = 0x03,
162 PWR_ERROR_CAP = 0x04,
163 PWR_FATAL_ERROR = 0x05,
164};
165
166/* UICCMD - UIC Command */
167#define COMMAND_OPCODE_MASK 0xFF
168#define GEN_SELECTOR_INDEX_MASK 0xFFFF
169
170#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
171#define RESET_LEVEL 0xFF
172
173#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
174#define CFG_RESULT_CODE_MASK 0xFF
175#define GENERIC_ERROR_CODE_MASK 0xFF
176
177/* GenSelectorIndex calculation macros for M-PHY attributes */
178#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
179#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
180
181#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
182 ((sel) & 0xFFFF))
183#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
184#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
185#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
186
187/* Link Status*/
188enum link_status {
189 UFSHCD_LINK_IS_DOWN = 1,
190 UFSHCD_LINK_IS_UP = 2,
191};
192
193#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
194 ((sel) & 0xFFFF))
195#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
196#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
197#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
198
199/* UIC Commands */
200enum uic_cmd_dme {
201 UIC_CMD_DME_GET = 0x01,
202 UIC_CMD_DME_SET = 0x02,
203 UIC_CMD_DME_PEER_GET = 0x03,
204 UIC_CMD_DME_PEER_SET = 0x04,
205 UIC_CMD_DME_POWERON = 0x10,
206 UIC_CMD_DME_POWEROFF = 0x11,
207 UIC_CMD_DME_ENABLE = 0x12,
208 UIC_CMD_DME_RESET = 0x14,
209 UIC_CMD_DME_END_PT_RST = 0x15,
210 UIC_CMD_DME_LINK_STARTUP = 0x16,
211 UIC_CMD_DME_HIBER_ENTER = 0x17,
212 UIC_CMD_DME_HIBER_EXIT = 0x18,
213 UIC_CMD_DME_TEST_MODE = 0x1A,
214};
215
216/* UIC Config result code / Generic error code */
217enum {
218 UIC_CMD_RESULT_SUCCESS = 0x00,
219 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
220 UIC_CMD_RESULT_FAILURE = 0x01,
221 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
222 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
223 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
224 UIC_CMD_RESULT_BAD_INDEX = 0x05,
225 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
226 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
227 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
228 UIC_CMD_RESULT_BUSY = 0x09,
229 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
230};
231
232#define MASK_UIC_COMMAND_RESULT 0xFF
233
234/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
235#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
236
237/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
238#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
239
240struct ufshcd_sg_entry {
241 __le32 base_addr;
242 __le32 upper_addr;
243 __le32 reserved;
244 __le32 size;
245};
246
247#define MAX_BUFF 128
248/**
249 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
250 * @command_upiu: Command UPIU Frame address
251 * @response_upiu: Response UPIU Frame address
252 * @prd_table: Physical Region Descriptor
253 */
254struct utp_transfer_cmd_desc {
255 u8 command_upiu[ALIGNED_UPIU_SIZE];
256 u8 response_upiu[ALIGNED_UPIU_SIZE];
257 struct ufshcd_sg_entry prd_table[MAX_BUFF];
258};
259
260/**
261 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
262 * @dword0: Descriptor Header DW0
263 * @dword1: Descriptor Header DW1
264 * @dword2: Descriptor Header DW2
265 * @dword3: Descriptor Header DW3
266 */
267struct request_desc_header {
268 __le32 dword_0;
269 __le32 dword_1;
270 __le32 dword_2;
271 __le32 dword_3;
272};
273
274/**
275 * struct utp_transfer_req_desc - UTRD structure
276 * @header: UTRD header DW-0 to DW-3
277 * @command_desc_base_addr_lo: UCD base address low DW-4
278 * @command_desc_base_addr_hi: UCD base address high DW-5
279 * @response_upiu_length: response UPIU length DW-6
280 * @response_upiu_offset: response UPIU offset DW-6
281 * @prd_table_length: Physical region descriptor length DW-7
282 * @prd_table_offset: Physical region descriptor offset DW-7
283 */
284struct utp_transfer_req_desc {
285 /* DW 0-3 */
286 struct request_desc_header header;
287
288 /* DW 4-5*/
289 __le32 command_desc_base_addr_lo;
290 __le32 command_desc_base_addr_hi;
291
292 /* DW 6 */
293 __le16 response_upiu_length;
294 __le16 response_upiu_offset;
295
296 /* DW 7 */
297 __le16 prd_table_length;
298 __le16 prd_table_offset;
299};
300
301/**
302 * struct utp_upiu_header - UPIU header structure
303 * @dword_0: UPIU header DW-0
304 * @dword_1: UPIU header DW-1
305 * @dword_2: UPIU header DW-2
306 */
307struct utp_upiu_header {
308 __be32 dword_0;
309 __be32 dword_1;
310 __be32 dword_2;
311};
312
313/*
314 * UTMRD structure.
315 */
316struct utp_task_req_desc {
317 /* DW 0-3 */
318 struct request_desc_header header;
319
320 /* DW 4-11 - Task request UPIU structure */
321 struct utp_upiu_header req_header;
322 __be32 input_param1;
323 __be32 input_param2;
324 __be32 input_param3;
325 __be32 __reserved1[2];
326
327 /* DW 12-19 - Task Management Response UPIU structure */
328 struct utp_upiu_header rsp_header;
329 __be32 output_param1;
330 __be32 output_param2;
331 __be32 __reserved2[3];
332};
333
334#endif