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Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +09001/*
2 * board/renesas/salvator-x/salvator-x.c
3 * This file is Salvator-X board support.
4 *
Marek Vasut5abb39b2017-05-13 15:57:46 +02005 * Copyright (C) 2015-2017 Renesas Electronics Corporation
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +09006 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <malloc.h>
13#include <netdev.h>
14#include <dm.h>
15#include <dm/platform_data/serial_sh.h>
16#include <asm/processor.h>
17#include <asm/mach-types.h>
18#include <asm/io.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090019#include <linux/errno.h>
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090020#include <asm/arch/sys_proto.h>
21#include <asm/gpio.h>
22#include <asm/arch/gpio.h>
23#include <asm/arch/rmobile.h>
24#include <asm/arch/rcar-mstp.h>
Marek Vasut5abb39b2017-05-13 15:57:46 +020025#include <asm/arch/sh_sdhi.h>
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090026#include <i2c.h>
27#include <mmc.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#define CPGWPCR 0xE6150904
32#define CPGWPR 0xE615090C
33
34#define CLK2MHZ(clk) (clk / 1000 / 1000)
35void s_init(void)
36{
37 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
38 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
39
40 /* Watchdog init */
41 writel(0xA5A5A500, &rwdt->rwtcsra);
42 writel(0xA5A5A500, &swdt->swtcsra);
43
44 writel(0xA5A50000, CPGWPCR);
45 writel(0xFFFFFFFF, CPGWPR);
46}
47
Marek Vasut3614d302017-05-13 15:57:41 +020048#define GSX_MSTP112 BIT(12) /* 3DG */
49#define TMU0_MSTP125 BIT(25) /* secure */
50#define TMU1_MSTP124 BIT(24) /* non-secure */
51#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
Marek Vasut51e80062017-05-13 15:57:47 +020052#define ETHERAVB_MSTP812 BIT(12)
Marek Vasutc16ed0b2017-05-13 15:57:48 +020053#define DVFS_MSTP926 BIT(26)
Marek Vasut5abb39b2017-05-13 15:57:46 +020054#define SD0_MSTP314 BIT(14)
55#define SD1_MSTP313 BIT(13)
56#define SD2_MSTP312 BIT(12) /* either MMC0 */
57#define SD3_MSTP311 BIT(11) /* either MMC1 */
58
59#define SD0CKCR 0xE6150074
60#define SD1CKCR 0xE6150078
61#define SD2CKCR 0xE6150268
62#define SD3CKCR 0xE615026C
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090063
64int board_early_init_f(void)
65{
66 /* TMU0,1 */ /* which use ? */
67 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
68 /* SCIF2 */
69 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
Marek Vasut51e80062017-05-13 15:57:47 +020070 /* EHTERAVB */
71 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
Marek Vasut5abb39b2017-05-13 15:57:46 +020072 /* eMMC */
73 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
74 /* SDHI0, 3 */
75 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
76
77 writel(0, SD0CKCR);
78 writel(0, SD1CKCR);
79 writel(0, SD2CKCR);
80 writel(0, SD3CKCR);
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090081
Marek Vasutc16ed0b2017-05-13 15:57:48 +020082#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
83 /* DVFS for reset */
84 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
85#endif
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090086 return 0;
87}
88
89/* SYSC */
90/* R/- 32 Power status register 2(3DG) */
91#define SYSC_PWRSR2 0xE6180100
92/* -/W 32 Power resume control register 2 (3DG) */
93#define SYSC_PWRONCR2 0xE618010C
94
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +090095int board_init(void)
96{
97 /* adress of boot parameters */
98 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
99
100 /* Init PFC controller */
101 r8a7795_pinmux_init();
102
103 /* GSX: force power and clock supply */
104 writel(0x0000001F, SYSC_PWRONCR2);
105 while (readl(SYSC_PWRSR2) != 0x000003E0)
106 mdelay(20);
107
108 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
109
Marek Vasut4659a622017-05-13 15:57:49 +0200110 /* USB1 pull-up */
111 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
112
Marek Vasut51e80062017-05-13 15:57:47 +0200113#ifdef CONFIG_RAVB
114 /* EtherAVB Enable */
115 /* GPSR2 */
116 gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
117 gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
118 gpio_request(GPIO_GFN_AVB_LINK, NULL);
119 gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
120 gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
121 gpio_request(GPIO_GFN_AVB_MDC, NULL);
122
123 /* IPSR0 */
124 gpio_request(GPIO_IFN_AVB_MDC, NULL);
125 gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
126 gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
127 gpio_request(GPIO_IFN_AVB_LINK, NULL);
128 gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
129 gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
130 /* IPSR1 */
131 gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
132 /* IPSR2 */
133 gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
134 /* IPSR3 */
135 gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
136
Marek Vasut4659a622017-05-13 15:57:49 +0200137 /* USB2_OVC */
138 gpio_request(GPIO_GP_6_15, NULL);
139 gpio_direction_input(GPIO_GP_6_15);
140
141 /* USB2_PWEN */
142 gpio_request(GPIO_GP_6_14, NULL);
143 gpio_direction_output(GPIO_GP_6_14, 1);
144 gpio_set_value(GPIO_GP_6_14, 1);
145
Marek Vasut51e80062017-05-13 15:57:47 +0200146 /* AVB_PHY_RST */
147 gpio_request(GPIO_GP_2_10, NULL);
148 gpio_direction_output(GPIO_GP_2_10, 0);
149 mdelay(20);
150 gpio_set_value(GPIO_GP_2_10, 1);
151 udelay(1);
152#endif
153
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900154 return 0;
155}
Marek Vasut5abb39b2017-05-13 15:57:46 +0200156
Marek Vasut51e80062017-05-13 15:57:47 +0200157static struct eth_pdata salvator_x_ravb_platdata = {
158 .iobase = 0xE6800000,
159 .phy_interface = 0,
160 .max_speed = 1000,
161};
162
163U_BOOT_DEVICE(salvator_x_ravb) = {
164 .name = "ravb",
165 .platdata = &salvator_x_ravb_platdata,
166};
167
Marek Vasut5abb39b2017-05-13 15:57:46 +0200168#ifdef CONFIG_SH_SDHI
169int board_mmc_init(bd_t *bis)
170{
171 int ret = -ENODEV;
172
173 /* SDHI0 */
174 gpio_request(GPIO_GFN_SD0_DAT0, NULL);
175 gpio_request(GPIO_GFN_SD0_DAT1, NULL);
176 gpio_request(GPIO_GFN_SD0_DAT2, NULL);
177 gpio_request(GPIO_GFN_SD0_DAT3, NULL);
178 gpio_request(GPIO_GFN_SD0_CLK, NULL);
179 gpio_request(GPIO_GFN_SD0_CMD, NULL);
180 gpio_request(GPIO_GFN_SD0_CD, NULL);
181 gpio_request(GPIO_GFN_SD0_WP, NULL);
182
183 gpio_request(GPIO_GP_5_2, NULL);
184 gpio_request(GPIO_GP_5_1, NULL);
185 gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
186 gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
187
188 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
189 SH_SDHI_QUIRK_64BIT_BUF);
190 if (ret)
191 return ret;
192
193 /* SDHI1/SDHI2 eMMC */
194 gpio_request(GPIO_GFN_SD1_DAT0, NULL);
195 gpio_request(GPIO_GFN_SD1_DAT1, NULL);
196 gpio_request(GPIO_GFN_SD1_DAT2, NULL);
197 gpio_request(GPIO_GFN_SD1_DAT3, NULL);
198 gpio_request(GPIO_GFN_SD2_DAT0, NULL);
199 gpio_request(GPIO_GFN_SD2_DAT1, NULL);
200 gpio_request(GPIO_GFN_SD2_DAT2, NULL);
201 gpio_request(GPIO_GFN_SD2_DAT3, NULL);
202 gpio_request(GPIO_GFN_SD2_CLK, NULL);
203 gpio_request(GPIO_GFN_SD2_CMD, NULL);
204 gpio_request(GPIO_GP_5_3, NULL);
205 gpio_request(GPIO_GP_5_9, NULL);
206 gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
207 gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
208
209 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
210 SH_SDHI_QUIRK_64BIT_BUF);
211 if (ret)
212 return ret;
213
214 /* SDHI3 */
215 gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
216 gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */
217 gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */
218 gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */
219 gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */
220 gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */
221 /* IPSR10 */
222 gpio_request(GPIO_FN_SD3_CD, NULL);
223 gpio_request(GPIO_FN_SD3_WP, NULL);
224
225 gpio_request(GPIO_GP_3_15, NULL);
226 gpio_request(GPIO_GP_3_14, NULL);
227 gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
228 gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
229
230 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
231 SH_SDHI_QUIRK_64BIT_BUF);
232 return ret;
233}
234#endif
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900235
236int dram_init(void)
237{
Marek Vasut3fca9d22017-05-13 15:57:50 +0200238 gd->ram_size = PHYS_SDRAM_1_SIZE;
239#if (CONFIG_NR_DRAM_BANKS >= 2)
240 gd->ram_size += PHYS_SDRAM_2_SIZE;
241#endif
242#if (CONFIG_NR_DRAM_BANKS >= 3)
243 gd->ram_size += PHYS_SDRAM_3_SIZE;
244#endif
245#if (CONFIG_NR_DRAM_BANKS >= 4)
246 gd->ram_size += PHYS_SDRAM_4_SIZE;
247#endif
248
249 return 0;
250}
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900251
Marek Vasut3fca9d22017-05-13 15:57:50 +0200252int dram_init_banksize(void)
253{
254 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
255 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
256#if (CONFIG_NR_DRAM_BANKS >= 2)
257 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
258 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
259#endif
260#if (CONFIG_NR_DRAM_BANKS >= 3)
261 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
262 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
263#endif
264#if (CONFIG_NR_DRAM_BANKS >= 4)
265 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
266 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
267#endif
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900268 return 0;
269}
270
271const struct rmobile_sysinfo sysinfo = {
272 CONFIG_RCAR_BOARD_STRING
273};
274
275#define RST_BASE 0xE6160000
276#define RST_CA57RESCNT (RST_BASE + 0x40)
277#define RST_CA53RESCNT (RST_BASE + 0x44)
278#define RST_RSTOUTCR (RST_BASE + 0x58)
279#define RST_CODE 0xA5A5000F
280
281void reset_cpu(ulong addr)
282{
Marek Vasutc16ed0b2017-05-13 15:57:48 +0200283#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
284 i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
285#else
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900286 /* only CA57 ? */
287 writel(RST_CODE, RST_CA57RESCNT);
Marek Vasutc16ed0b2017-05-13 15:57:48 +0200288#endif
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900289}
290
291static const struct sh_serial_platdata serial_platdata = {
292 .base = SCIF2_BASE,
293 .type = PORT_SCIF,
Marek Vasutff178222017-05-13 15:57:45 +0200294 .clk = CONFIG_SH_SCIF_CLK_FREQ,
295 .clk_mode = INT_CLK,
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900296};
297
298U_BOOT_DEVICE(salvator_x_scif2) = {
299 .name = "serial_sh",
300 .platdata = &serial_platdata,
301};