| Masahiro Yamada | d5f8fee | 2015-03-12 13:24:39 +0900 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 2 | CONFIG_ARCH_SOCFPGA=y |
| Masahiro Yamada | d5f8fee | 2015-03-12 13:24:39 +0900 | [diff] [blame] | 3 | CONFIG_TARGET_SOCFPGA_CYCLONE5=y |
| Marek Vasut | 8656583 | 2014-12-30 21:05:53 +0100 | [diff] [blame] | 4 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" |
| Joe Hershberger | a274ded | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 5 | CONFIG_SPL=y |
| Joe Hershberger | 5a9d7f1 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 6 | # CONFIG_CMD_IMLS is not set |
| 7 | # CONFIG_CMD_FLASH is not set |
| Joe Hershberger | a274ded | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 8 | CONFIG_OF_CONTROL=y |
| Masahiro Yamada | 1e35f39 | 2015-08-12 07:31:54 +0900 | [diff] [blame] | 9 | CONFIG_SPL_OF_CONTROL=y |
| Joe Hershberger | 17491a8 | 2015-06-22 16:15:29 -0500 | [diff] [blame] | 10 | CONFIG_SPI_FLASH=y |
| Marek Vasut | 5ca9954 | 2015-07-25 18:47:02 +0200 | [diff] [blame] | 11 | CONFIG_DM_ETH=y |
| Joe Hershberger | 17491a8 | 2015-06-22 16:15:29 -0500 | [diff] [blame] | 12 | CONFIG_NETDEVICES=y |
| Simon Glass | 6e37874 | 2015-04-05 16:07:34 -0600 | [diff] [blame] | 13 | CONFIG_ETH_DESIGNWARE=y |
| Marek Vasut | 1029caf | 2015-07-10 00:04:23 +0200 | [diff] [blame] | 14 | CONFIG_SPL_DM=y |
| 15 | CONFIG_SPL_MMC_SUPPORT=y |
| Marek Vasut | cadf2f9 | 2015-07-21 07:50:03 +0200 | [diff] [blame] | 16 | CONFIG_DM_SEQ_ALIAS=y |
| 17 | CONFIG_SPL_SIMPLE_BUS=y |
| 18 | CONFIG_DM_SPI=y |
| 19 | CONFIG_DM_SPI_FLASH=y |
| 20 | CONFIG_SPL_SPI_SUPPORT=y |
| Marek Vasut | ffb8e7f | 2015-07-12 15:23:28 +0200 | [diff] [blame] | 21 | CONFIG_SPL_STACK_R=y |
| 22 | CONFIG_SPL_STACK_R_ADDR=0x00800000 |
| 23 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |