| Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Freescale i.MX28 OCOTP Register Definitions |
| 3 | * |
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
| 5 | * on behalf of DENX Software Engineering GmbH |
| 6 | * |
| 7 | * Based on code from LTIB: |
| 8 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 23 | * |
| 24 | */ |
| 25 | |
| 26 | #ifndef __MX28_REGS_OCOTP_H__ |
| 27 | #define __MX28_REGS_OCOTP_H__ |
| 28 | |
| 29 | #include <asm/arch/regs-common.h> |
| 30 | |
| 31 | #ifndef __ASSEMBLY__ |
| 32 | struct mx28_ocotp_regs { |
| Otavio Salvador | 5309b00 | 2012-08-05 09:05:30 +0000 | [diff] [blame^] | 33 | mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */ |
| 34 | mxs_reg_32(hw_ocotp_data) /* 0x10 */ |
| 35 | mxs_reg_32(hw_ocotp_cust0) /* 0x20 */ |
| 36 | mxs_reg_32(hw_ocotp_cust1) /* 0x30 */ |
| 37 | mxs_reg_32(hw_ocotp_cust2) /* 0x40 */ |
| 38 | mxs_reg_32(hw_ocotp_cust3) /* 0x50 */ |
| 39 | mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */ |
| 40 | mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */ |
| 41 | mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */ |
| 42 | mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */ |
| 43 | mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ |
| 44 | mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ |
| 45 | mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ |
| 46 | mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ |
| 47 | mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ |
| 48 | mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ |
| 49 | mxs_reg_32(hw_ocotp_swcap) /* 0x100 */ |
| 50 | mxs_reg_32(hw_ocotp_custcap) /* 0x110 */ |
| 51 | mxs_reg_32(hw_ocotp_lock) /* 0x120 */ |
| 52 | mxs_reg_32(hw_ocotp_ops0) /* 0x130 */ |
| 53 | mxs_reg_32(hw_ocotp_ops1) /* 0x140 */ |
| 54 | mxs_reg_32(hw_ocotp_ops2) /* 0x150 */ |
| 55 | mxs_reg_32(hw_ocotp_ops3) /* 0x160 */ |
| 56 | mxs_reg_32(hw_ocotp_un0) /* 0x170 */ |
| 57 | mxs_reg_32(hw_ocotp_un1) /* 0x180 */ |
| 58 | mxs_reg_32(hw_ocotp_un2) /* 0x190 */ |
| 59 | mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */ |
| 60 | mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */ |
| 61 | mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */ |
| 62 | mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */ |
| 63 | mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */ |
| 64 | mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */ |
| 65 | mxs_reg_32(hw_ocotp_rom6) /* 0x200 */ |
| 66 | mxs_reg_32(hw_ocotp_rom7) /* 0x210 */ |
| 67 | mxs_reg_32(hw_ocotp_srk0) /* 0x220 */ |
| 68 | mxs_reg_32(hw_ocotp_srk1) /* 0x230 */ |
| 69 | mxs_reg_32(hw_ocotp_srk2) /* 0x240 */ |
| 70 | mxs_reg_32(hw_ocotp_srk3) /* 0x250 */ |
| 71 | mxs_reg_32(hw_ocotp_srk4) /* 0x260 */ |
| 72 | mxs_reg_32(hw_ocotp_srk5) /* 0x270 */ |
| 73 | mxs_reg_32(hw_ocotp_srk6) /* 0x280 */ |
| 74 | mxs_reg_32(hw_ocotp_srk7) /* 0x290 */ |
| 75 | mxs_reg_32(hw_ocotp_version) /* 0x2a0 */ |
| Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 76 | }; |
| 77 | #endif |
| 78 | |
| 79 | #define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) |
| 80 | #define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 |
| 81 | #define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) |
| 82 | #define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) |
| 83 | #define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) |
| 84 | #define OCOTP_CTRL_ERROR (1 << 9) |
| 85 | #define OCOTP_CTRL_BUSY (1 << 8) |
| 86 | #define OCOTP_CTRL_ADDR_MASK 0x3f |
| 87 | #define OCOTP_CTRL_ADDR_OFFSET 0 |
| 88 | |
| 89 | #define OCOTP_DATA_DATA_MASK 0xffffffff |
| 90 | #define OCOTP_DATA_DATA_OFFSET 0 |
| 91 | |
| 92 | #define OCOTP_CUST_BITS_MASK 0xffffffff |
| 93 | #define OCOTP_CUST_BITS_OFFSET 0 |
| 94 | |
| 95 | #define OCOTP_CRYPTO_BITS_MASK 0xffffffff |
| 96 | #define OCOTP_CRYPTO_BITS_OFFSET 0 |
| 97 | |
| 98 | #define OCOTP_HWCAP_BITS_MASK 0xffffffff |
| 99 | #define OCOTP_HWCAP_BITS_OFFSET 0 |
| 100 | |
| 101 | #define OCOTP_SWCAP_BITS_MASK 0xffffffff |
| 102 | #define OCOTP_SWCAP_BITS_OFFSET 0 |
| 103 | |
| 104 | #define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) |
| 105 | #define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) |
| 106 | |
| 107 | #define OCOTP_LOCK_ROM7 (1 << 31) |
| 108 | #define OCOTP_LOCK_ROM6 (1 << 30) |
| 109 | #define OCOTP_LOCK_ROM5 (1 << 29) |
| 110 | #define OCOTP_LOCK_ROM4 (1 << 28) |
| 111 | #define OCOTP_LOCK_ROM3 (1 << 27) |
| 112 | #define OCOTP_LOCK_ROM2 (1 << 26) |
| 113 | #define OCOTP_LOCK_ROM1 (1 << 25) |
| 114 | #define OCOTP_LOCK_ROM0 (1 << 24) |
| 115 | #define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) |
| 116 | #define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) |
| 117 | #define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) |
| 118 | #define OCOTP_LOCK_PIN (1 << 20) |
| 119 | #define OCOTP_LOCK_OPS (1 << 19) |
| 120 | #define OCOTP_LOCK_UN2 (1 << 18) |
| 121 | #define OCOTP_LOCK_UN1 (1 << 17) |
| 122 | #define OCOTP_LOCK_UN0 (1 << 16) |
| 123 | #define OCOTP_LOCK_SRK (1 << 15) |
| 124 | #define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) |
| 125 | #define OCOTP_LOCK_UNALLOCATED_OFFSET 12 |
| 126 | #define OCOTP_LOCK_SRK_SHADOW (1 << 11) |
| 127 | #define OCOTP_LOCK_ROM_SHADOW (1 << 10) |
| 128 | #define OCOTP_LOCK_CUSTCAP (1 << 9) |
| 129 | #define OCOTP_LOCK_HWSW (1 << 8) |
| 130 | #define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) |
| 131 | #define OCOTP_LOCK_HWSW_SHADOW (1 << 6) |
| 132 | #define OCOTP_LOCK_CRYPTODCP (1 << 5) |
| 133 | #define OCOTP_LOCK_CRYPTOKEY (1 << 4) |
| 134 | #define OCOTP_LOCK_CUST3 (1 << 3) |
| 135 | #define OCOTP_LOCK_CUST2 (1 << 2) |
| 136 | #define OCOTP_LOCK_CUST1 (1 << 1) |
| 137 | #define OCOTP_LOCK_CUST0 (1 << 0) |
| 138 | |
| 139 | #define OCOTP_OPS_BITS_MASK 0xffffffff |
| 140 | #define OCOTP_OPS_BITS_OFFSET 0 |
| 141 | |
| 142 | #define OCOTP_UN_BITS_MASK 0xffffffff |
| 143 | #define OCOTP_UN_BITS_OFFSET 0 |
| 144 | |
| 145 | #define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24) |
| 146 | #define OCOTP_ROM_BOOT_MODE_OFFSET 24 |
| 147 | #define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22) |
| 148 | #define OCOTP_ROM_SD_MMC_MODE_OFFSET 22 |
| 149 | #define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20) |
| 150 | #define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20 |
| 151 | #define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14) |
| 152 | #define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14 |
| 153 | #define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12) |
| 154 | #define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 |
| 155 | #define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) |
| 156 | #define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 |
| 157 | #define OCOTP_ROM_EMMC_USE_DDR (1 << 7) |
| 158 | #define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) |
| 159 | #define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) |
| 160 | #define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) |
| 161 | #define OCOTP_ROM_SD_MBR_BOOT (1 << 3) |
| 162 | |
| 163 | #define OCOTP_SRK_BITS_MASK 0xffffffff |
| 164 | #define OCOTP_SRK_BITS_OFFSET 0 |
| 165 | |
| 166 | #define OCOTP_VERSION_MAJOR_MASK (0xff << 24) |
| 167 | #define OCOTP_VERSION_MAJOR_OFFSET 24 |
| 168 | #define OCOTP_VERSION_MINOR_MASK (0xff << 16) |
| 169 | #define OCOTP_VERSION_MINOR_OFFSET 16 |
| 170 | #define OCOTP_VERSION_STEP_MASK 0xffff |
| 171 | #define OCOTP_VERSION_STEP_OFFSET 0 |
| 172 | |
| 173 | #endif /* __MX28_REGS_OCOTP_H__ */ |