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git01.mediatek.com / filogic / uboot / 30e055ba629e42cf8ece93759a700d1c4da01280 / . / board / renesas / sh7785lcr / lowlevel_init.S
blob: f5ebeb9a7d8edc953debe92f2684ad7eaf26aae7 [file] [log] [blame]
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900[diff] [blame]1/*
2 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19#include <config.h>
20#include <version.h>
21#include <asm/processor.h>
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]22#include <asm/macro.h>
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900[diff] [blame]23
24#include <asm/processor.h>
25
26 .global lowlevel_init
27
28 .text
29 .align 2
30
31lowlevel_init:
32 wait_timer WAIT_200US
33 wait_timer WAIT_200US
34
35 /*------- LBSC -------*/
36 write32 MMSELR_A, MMSELR_D
37
38 /*------- DBSC2 -------*/
39 write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
40 write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
41 write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
42 write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
43 write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
44 write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
45 wait_timer WAIT_200US
46
47 write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
48 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
49 wait_timer WAIT_200US
50 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
51 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
52 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
53 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
54 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
55 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
56 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
57 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
58 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
59 wait_timer WAIT_200US
60
61 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
62 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
63
64 write32 DBSC2_DBEN_A, DBSC2_DBEN_D
65 write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
66 write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
67 write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
68 wait_timer WAIT_200US
69
70 /*------- GPIO -------*/
71 write16 PACR_A, PACR_D
72 write16 PBCR_A, PBCR_D
73 write16 PCCR_A, PCCR_D
74 write16 PDCR_A, PDCR_D
75 write16 PECR_A, PECR_D
76 write16 PFCR_A, PFCR_D
77 write16 PGCR_A, PGCR_D
78 write16 PHCR_A, PHCR_D
79 write16 PJCR_A, PJCR_D
80 write16 PKCR_A, PKCR_D
81 write16 PLCR_A, PLCR_D
82 write16 PMCR_A, PMCR_D
83 write16 PNCR_A, PNCR_D
84 write16 PPCR_A, PPCR_D
85 write16 PQCR_A, PQCR_D
86 write16 PRCR_A, PRCR_D
87
88 write8 PEPUPR_A, PEPUPR_D
89 write8 PHPUPR_A, PHPUPR_D
90 write8 PJPUPR_A, PJPUPR_D
91 write8 PKPUPR_A, PKPUPR_D
92 write8 PLPUPR_A, PLPUPR_D
93 write8 PMPUPR_A, PMPUPR_D
94 write8 PNPUPR_A, PNPUPR_D
95 write16 PPUPR1_A, PPUPR1_D
96 write16 PPUPR2_A, PPUPR2_D
97 write16 P1MSELR_A, P1MSELR_D
98 write16 P2MSELR_A, P2MSELR_D
99
100 /*------- LBSC -------*/
101 write32 BCR_A, BCR_D
102 write32 CS0BCR_A, CS0BCR_D
103 write32 CS0WCR_A, CS0WCR_D
104 write32 CS1BCR_A, CS1BCR_D
105 write32 CS1WCR_A, CS1WCR_D
106 write32 CS4BCR_A, CS4BCR_D
107 write32 CS4WCR_A, CS4WCR_D
108
109 mov.l PASCR_A, r0
110 mov.l @r0, r2
111 mov.l PASCR_32BIT_MODE, r1
112 tst r1, r2
113 bt lbsc_29bit
114
115 write32 CS2BCR_A, CS_USB_BCR_D
116 write32 CS2WCR_A, CS_USB_WCR_D
117 write32 CS3BCR_A, CS_SD_BCR_D
118 write32 CS3WCR_A, CS_SD_WCR_D
119 write32 CS5BCR_A, CS_I2C_BCR_D
120 write32 CS5WCR_A, CS_I2C_WCR_D
121 write32 CS6BCR_A, CS0BCR_D
122 write32 CS6WCR_A, CS0WCR_D
123 bra lbsc_end
124 nop
125
126lbsc_29bit:
127 write32 CS5BCR_A, CS_USB_BCR_D
128 write32 CS5WCR_A, CS_USB_WCR_D
129 write32 CS6BCR_A, CS_SD_BCR_D
130 write32 CS6WCR_A, CS_SD_WCR_D
131
132lbsc_end:
133
134 write32 CCR_A, CCR_D
135
136 rts
137 nop
138
139 .align 4
140
141/*------- LBSC -------*/
142MMSELR_A: .long 0xfc400020
143MMSELR_D: .long 0xa5a50002
144
145/*------- DBSC2 -------*/
146#define DBSC2_BASE 0xfe800000
147DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
148DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
149DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
150DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
151DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
152DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
153DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
154DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
155DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
156DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
157DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
158DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
159DBSC2_DBDICODTOCD_A: .long DBSC2_BASE + 0x54
160DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
161DDR_DUMMY_ACCESS_A: .long 0x40000000
162
163DBSC2_DBCONF_D: .long 0x00630002
164DBSC2_DBTR0_D: .long 0x050b1f04
165DBSC2_DBTR1_D: .long 0x00040204
166DBSC2_DBTR2_D: .long 0x02100308
167DBSC2_DBFREQ_D1: .long 0x00000000
168DBSC2_DBFREQ_D2: .long 0x00000100
169DBSC2_DBDICODTOCD_D: .long 0x000f0907
170
171DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
172DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
173DBSC2_DBCMDCNT_D_REF: .long 0x00000004
174
175DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
176DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
177DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
178DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
179DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
180DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
181
182DBSC2_DBEN_D: .long 0x00000001
183
184DBSC2_DBPDCNT0_D3: .long 0x00000080
185DBSC2_DBRFCNT1_D: .long 0x00000926
186DBSC2_DBRFCNT2_D: .long 0x00fe00fe
187DBSC2_DBRFCNT0_D: .long 0x00010000
188
189WAIT_200US: .long 33333
190
191/*------- GPIO -------*/
192#define GPIO_BASE 0xffe70000
193PACR_A: .long GPIO_BASE + 0x00
194PBCR_A: .long GPIO_BASE + 0x02
195PCCR_A: .long GPIO_BASE + 0x04
196PDCR_A: .long GPIO_BASE + 0x06
197PECR_A: .long GPIO_BASE + 0x08
198PFCR_A: .long GPIO_BASE + 0x0a
199PGCR_A: .long GPIO_BASE + 0x0c
200PHCR_A: .long GPIO_BASE + 0x0e
201PJCR_A: .long GPIO_BASE + 0x10
202PKCR_A: .long GPIO_BASE + 0x12
203PLCR_A: .long GPIO_BASE + 0x14
204PMCR_A: .long GPIO_BASE + 0x16
205PNCR_A: .long GPIO_BASE + 0x18
206PPCR_A: .long GPIO_BASE + 0x1a
207PQCR_A: .long GPIO_BASE + 0x1c
208PRCR_A: .long GPIO_BASE + 0x1e
209PEPUPR_A: .long GPIO_BASE + 0x48
210PHPUPR_A: .long GPIO_BASE + 0x4e
211PJPUPR_A: .long GPIO_BASE + 0x50
212PKPUPR_A: .long GPIO_BASE + 0x52
213PLPUPR_A: .long GPIO_BASE + 0x54
214PMPUPR_A: .long GPIO_BASE + 0x56
215PNPUPR_A: .long GPIO_BASE + 0x58
216PPUPR1_A: .long GPIO_BASE + 0x60
217PPUPR2_A: .long GPIO_BASE + 0x62
218P1MSELR_A: .long GPIO_BASE + 0x80
219P2MSELR_A: .long GPIO_BASE + 0x82
220
221PACR_D: .long 0x0000
222PBCR_D: .long 0x0000
223PCCR_D: .long 0x0000
224PDCR_D: .long 0x0000
225PECR_D: .long 0x0000
226PFCR_D: .long 0x0000
227PGCR_D: .long 0x0000
228PHCR_D: .long 0x00c0
229PJCR_D: .long 0xc3fc
230PKCR_D: .long 0x03ff
231PLCR_D: .long 0x0000
232PMCR_D: .long 0xffff
233PNCR_D: .long 0xf0c3
234PPCR_D: .long 0x0000
235PQCR_D: .long 0x0000
236PRCR_D: .long 0x0000
237
238PEPUPR_D: .long 0xff
239PHPUPR_D: .long 0x00
240PJPUPR_D: .long 0x00
241PKPUPR_D: .long 0x00
242PLPUPR_D: .long 0x00
243PMPUPR_D: .long 0xfc
244PNPUPR_D: .long 0x00
245PPUPR1_D: .long 0xffbf
246PPUPR2_D: .long 0xff00
247P1MSELR_D: .long 0x3780
248P2MSELR_D: .long 0x0000
249
250/*------- LBSC -------*/
251PASCR_A: .long 0xff000070
252PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
253
254BCR_A: .long BCR
255CS0BCR_A: .long CS0BCR
256CS0WCR_A: .long CS0WCR
257CS1BCR_A: .long CS1BCR
258CS1WCR_A: .long CS1WCR
259CS2BCR_A: .long CS2BCR
260CS2WCR_A: .long CS2WCR
261CS3BCR_A: .long CS3BCR
262CS3WCR_A: .long CS3WCR
263CS4BCR_A: .long CS4BCR
264CS4WCR_A: .long CS4WCR
265CS5BCR_A: .long CS5BCR
266CS5WCR_A: .long CS5WCR
267CS6BCR_A: .long CS6BCR
268CS6WCR_A: .long CS6WCR
269
270BCR_D: .long 0x80000003
271CS0BCR_D: .long 0x22222340
272CS0WCR_D: .long 0x00111118
273CS1BCR_D: .long 0x11111100
274CS1WCR_D: .long 0x33333303
275CS4BCR_D: .long 0x11111300
276CS4WCR_D: .long 0x00101012
277
278/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
279CS_USB_BCR_D: .long 0x11111200
280CS_USB_WCR_D: .long 0x00020004
281
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]282/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900[diff] [blame]283CS_SD_BCR_D: .long 0x00000300
284CS_SD_WCR_D: .long 0x00030108
285
286/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
287CS_I2C_BCR_D: .long 0x11111100
288CS_I2C_WCR_D: .long 0x00000003
289
290CCR_A: .long 0xff00001c
291CCR_D: .long 0x0000090b