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git01.mediatek.com / filogic / uboot / 213c0ebef75dd7e5cdebee744021d942c9bc3509 / . / arch / powerpc / cpu / mpc85xx / t4240_serdes.c
blob: c001780ca969c5cacd06d734e252d666f48627ea [file] [log] [blame]
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/fsl_serdes.h>
25#include <asm/processor.h>
26#include <asm/io.h>
27#include "fsl_corenet2_serdes.h"
28
29struct serdes_config {
30 u32 protocol;
31 u8 lanes[SRDS_MAX_LANES];
32};
33
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]34#ifdef CONFIG_PPC_T4240
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]35static const struct serdes_config serdes1_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]36 /* SerDes 1 */
37 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
38 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
39 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
40 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
41 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
42 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
43 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
44 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
45 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
46 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
47 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
48 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
49 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
50 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
51 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
52 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
53 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
54 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
55 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
56 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
57 {38, {NONE, NONE, QSGMII_FM1_B, NONE,
58 NONE, NONE, QSGMII_FM1_A, NONE}},
59 {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
60 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
61 NONE, NONE, QSGMII_FM1_A, NONE}},
62 {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
63 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
64 NONE, NONE, QSGMII_FM1_A, NONE}},
65 {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
66 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
67 NONE, NONE, QSGMII_FM1_A, NONE}},
68 {}
69};
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]70static const struct serdes_config serdes2_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]71 /* SerDes 2 */
72 {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
73 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
74 XAUI_FM2_MAC10, XAUI_FM2_MAC10,
75 XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
76 {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
77 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
78 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
79 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
80 {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
81 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
82 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
83 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
84 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
85 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
86 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
87 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
88 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
89 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
90 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
91 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
92 {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
93 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
94 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
95 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
96 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
97 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
98 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
99 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
100 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
101 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
102 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
103 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
104 {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
105 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
106 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
107 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
108 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
109 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
110 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
111 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
112 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
113 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
114 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
115 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
116 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
117 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
118 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
119 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
120 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
121 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
122 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
123 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
124 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
125 NONE, NONE, QSGMII_FM1_A, NONE}},
126 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
127 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
128 NONE, NONE, QSGMII_FM1_A, NONE}},
129 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
130 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
131 NONE, NONE, QSGMII_FM1_A, NONE}},
132 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
133 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
134 NONE, NONE, QSGMII_FM1_A, NONE}},
135 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
136 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
137 NONE, NONE, QSGMII_FM1_A, NONE}},
138 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
139 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
140 NONE, NONE, QSGMII_FM1_A, NONE}},
141 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
142 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
143 NONE, NONE, QSGMII_FM1_A, NONE}},
144 {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
145 XFI_FM2_MAC10, XFI_FM2_MAC9,
146 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
147 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
148 {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
149 XFI_FM2_MAC10, XFI_FM2_MAC9,
150 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
151 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
152 {}
153};
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]154static const struct serdes_config serdes3_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]155 /* SerDes 3 */
156 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
157 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
158 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
159 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
160 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
161 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
162 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
163 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
164 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
165 PCIE2, PCIE2, PCIE2, PCIE2}},
166 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
167 PCIE2, PCIE2, PCIE2, PCIE2}},
168 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
169 SRIO1, SRIO1, SRIO1, SRIO1}},
170 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
171 SRIO1, SRIO1, SRIO1, SRIO1}},
172 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
173 SRIO1, SRIO1, SRIO1, SRIO1}},
174 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
175 SRIO1, SRIO1, SRIO1, SRIO1}},
176 {}
177};
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]178static const struct serdes_config serdes4_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]179 /* SerDes 4 */
180 {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
181 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
182 {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
183 {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
Roy Zangcc117ce2013-03-25 07:33:18 +0000[diff] [blame]184 {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
185 {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]186 {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
187 {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
188 {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
189 {}
190};
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]191#elif defined(CONFIG_PPC_T4160)
192static const struct serdes_config serdes1_cfg_tbl[] = {
193 /* SerDes 1 */
194 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
195 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
196 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
197 XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
198 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
199 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
200 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
201 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
202 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
203 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
204 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
205 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
206 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
207 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
208 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
209 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
210 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
211 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
212 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
213 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
214 {38, {NONE, NONE, QSGMII_FM1_B, NONE,
215 NONE, NONE, QSGMII_FM1_A, NONE} },
216 {}
217};
218static const struct serdes_config serdes2_cfg_tbl[] = {
219 /* SerDes 2 */
220 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
221 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
222 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
223 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
224 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
225 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
226 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
227 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
228 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
229 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
230 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
231 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
232 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
233 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
234 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
235 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
236 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
237 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
238 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
239 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
240 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
241 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
242 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
243 NONE, NONE} },
244 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
245 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
246 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
247 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
248 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
249 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
250 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
251 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
252 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
253 NONE, QSGMII_FM1_A, NONE, NONE} },
254 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
255 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
256 NONE, QSGMII_FM1_A, NONE, NONE} },
257 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
258 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
259 NONE, QSGMII_FM1_A, NONE, NONE} },
260 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
261 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
262 NONE, QSGMII_FM1_A, NONE, NONE} },
263 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
264 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
265 NONE, NONE, NONE, NONE} },
266 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
267 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
268 NONE, NONE, NONE, NONE} },
269 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
270 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
271 NONE, NONE, NONE, NONE} },
272 {56, {NONE, XFI_FM1_MAC10,
273 XFI_FM2_MAC10, NONE,
274 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
275 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
276 {57, {NONE, XFI_FM1_MAC10,
277 XFI_FM2_MAC10, NONE,
278 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
279 NONE, NONE} },
280 {}
281};
282static const struct serdes_config serdes3_cfg_tbl[] = {
283 /* SerDes 3 */
284 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
285 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
286 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
287 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
288 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
289 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
290 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
291 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
292 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
293 PCIE2, PCIE2, PCIE2, PCIE2} },
294 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
295 PCIE2, PCIE2, PCIE2, PCIE2} },
296 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
297 SRIO1, SRIO1, SRIO1, SRIO1} },
298 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
299 SRIO1, SRIO1, SRIO1, SRIO1} },
300 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
301 SRIO1, SRIO1, SRIO1, SRIO1} },
302 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
303 NONE, NONE, NONE, NONE} },
304 {}
305};
306static const struct serdes_config serdes4_cfg_tbl[] = {
307 /* SerDes 4 */
308 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
309 {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
310 {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
311 {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
312 {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
313 {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
314 {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
315 {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
316 {}
317}
318;
319#else
320#error "Need to define SerDes protocol"
321#endif
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]322static const struct serdes_config *serdes_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]323 serdes1_cfg_tbl,
324 serdes2_cfg_tbl,
325 serdes3_cfg_tbl,
326 serdes4_cfg_tbl,
327};
328
329enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
330{
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]331 const struct serdes_config *ptr;
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]332
333 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
334 return 0;
335
336 ptr = serdes_cfg_tbl[serdes];
337 while (ptr->protocol) {
338 if (ptr->protocol == cfg)
339 return ptr->lanes[lane];
340 ptr++;
341 }
342 return 0;
343}
344
345int is_serdes_prtcl_valid(int serdes, u32 prtcl)
346{
347 int i;
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]348 const struct serdes_config *ptr;
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]349
350 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
351 return 0;
352
353 ptr = serdes_cfg_tbl[serdes];
354 while (ptr->protocol) {
355 if (ptr->protocol == prtcl)
356 break;
357 ptr++;
358 }
359
360 if (!ptr->protocol)
361 return 0;
362
363 for (i = 0; i < SRDS_MAX_LANES; i++) {
364 if (ptr->lanes[i] != NONE)
365 return 1;
366 }
367
368 return 0;
369}