Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 20a9004f7a335da173d96b97b41b518ce2dc5410 / . / arch / arm / dts / k3-j721e-common-proc-board-u-boot.dtsi
blob: 540c847eb38b3d40a26952006d065c5c4c9d17c5 [file] [log] [blame]
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]6#include <dt-bindings/net/ti-dp83867.h>
Neha Malcom Francis20a90042023-07-22 00:14:28 +0530[diff] [blame^]7#include "k3-j721e-binman.dtsi"
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]8
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]9/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
12 tick-timer = &timer1;
13 };
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]14
15 aliases {
16 ethernet0 = &cpsw_port1;
Lokesh Vutla62eada12021-02-01 11:26:40 +0530[diff] [blame]17 spi0 = &ospi0;
18 spi1 = &ospi1;
19 remoteproc0 = &mcu_r5fss0_core0;
20 remoteproc1 = &mcu_r5fss0_core1;
21 remoteproc2 = &main_r5fss0_core0;
22 remoteproc3 = &main_r5fss0_core1;
23 remoteproc4 = &main_r5fss1_core0;
24 remoteproc5 = &main_r5fss1_core1;
25 remoteproc6 = &c66_0;
26 remoteproc7 = &c66_1;
27 remoteproc8 = &c71_0;
28 i2c0 = &wkup_i2c0;
29 i2c1 = &mcu_i2c0;
30 i2c2 = &mcu_i2c1;
31 i2c3 = &main_i2c0;
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]32 };
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]33};
34
35&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Lokesh Vutla62eada12021-02-01 11:26:40 +0530[diff] [blame]37
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]38 main_navss: bus@30000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Lokesh Vutla62eada12021-02-01 11:26:40 +0530[diff] [blame]40 };
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]41};
42
43&cbass_mcu_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]45
46 timer1: timer@40400000 {
47 compatible = "ti,omap5430-timer";
48 reg = <0x0 0x40400000 0x0 0x80>;
49 ti,timer-alwon;
Tero Kristo94388c82021-06-11 11:45:27 +0300[diff] [blame]50 clock-frequency = <250000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]52 };
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]53
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]54 mcu_navss: bus@28380000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]56
Vignesh Raghavendra01250d82020-07-07 13:43:35 +0530[diff] [blame]57 ringacc@2b800000 {
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]58 reg = <0x0 0x2b800000 0x0 0x400000>,
59 <0x0 0x2b000000 0x0 0x400000>,
60 <0x0 0x28590000 0x0 0x100>,
61 <0x0 0x2a500000 0x0 0x40000>,
62 <0x0 0x28440000 0x0 0x40000>;
63 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]65 };
66
Vignesh Raghavendra01250d82020-07-07 13:43:35 +0530[diff] [blame]67 dma-controller@285c0000 {
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]68 reg = <0x0 0x285c0000 0x0 0x100>,
69 <0x0 0x284c0000 0x0 0x4000>,
70 <0x0 0x2a800000 0x0 0x40000>,
71 <0x0 0x284a0000 0x0 0x4000>,
72 <0x0 0x2aa00000 0x0 0x40000>,
73 <0x0 0x28400000 0x0 0x2000>;
74 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
75 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]77 };
78 };
Lokesh Vutla62eada12021-02-01 11:26:40 +0530[diff] [blame]79
80 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Lokesh Vutla62eada12021-02-01 11:26:40 +0530[diff] [blame]82 };
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]83};
84
85&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]87};
88
89&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]91 k3_sysreset: sysreset-controller {
92 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]94 };
95};
96
97&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]99};
100
101&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]103};
104
105&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]107};
108
109&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]111};
112
113&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]115};
116
117&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]119};
120
121&mcu_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]122 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]123};
124
125&main_sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]127};
128
129&main_sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]130 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]131};
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]132
Kishon Vijay Abraham I7f3a3092021-07-21 21:28:40 +0530[diff] [blame]133&wiz3_pll1_refclk {
134 assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
135 assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
136};
137
Vignesh Raghavendra04ed4932019-11-18 19:16:35 +0530[diff] [blame]138&main_usbss0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]139 bootph-pre-ram;
Vignesh Raghavendra04ed4932019-11-18 19:16:35 +0530[diff] [blame]140};
141
142&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]143 bootph-pre-ram;
Vignesh Raghavendra04ed4932019-11-18 19:16:35 +0530[diff] [blame]144};
145
146&usb0 {
147 dr_mode = "peripheral";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]148 bootph-pre-ram;
Vignesh Raghavendra04ed4932019-11-18 19:16:35 +0530[diff] [blame]149};
150
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]151&mcu_cpsw {
152 reg = <0x0 0x46000000 0x0 0x200000>,
153 <0x0 0x40f00200 0x0 0x2>;
154 reg-names = "cpsw_nuss", "mac_efuse";
Vignesh Raghavendra3f09ed42020-07-06 13:36:55 +0530[diff] [blame]155 /delete-property/ ranges;
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]156
157 cpsw-phy-sel@40f04040 {
158 compatible = "ti,am654-cpsw-phy-sel";
159 reg= <0x0 0x40f04040 0x0 0x4>;
160 reg-names = "gmii-sel";
161 };
162};
Faiz Abbasc67d3892020-01-16 19:42:21 +0530[diff] [blame]163
164&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]165 bootph-pre-ram;
Faiz Abbasc67d3892020-01-16 19:42:21 +0530[diff] [blame]166};
Andreas Dannenberg0fe40e92020-01-07 13:15:56 +0530[diff] [blame]167
168&wkup_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]169 bootph-pre-ram;
Andreas Dannenberg0fe40e92020-01-07 13:15:56 +0530[diff] [blame]170};
171
172&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]173 bootph-pre-ram;
Andreas Dannenberg0fe40e92020-01-07 13:15:56 +0530[diff] [blame]174};
Vignesh Raghavendra8a290cc2020-01-27 23:22:15 +0530[diff] [blame]175
176&main_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]177 bootph-pre-ram;
Vignesh Raghavendra8a290cc2020-01-27 23:22:15 +0530[diff] [blame]178};
179
180&main_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]181 bootph-pre-ram;
Vignesh Raghavendra8a290cc2020-01-27 23:22:15 +0530[diff] [blame]182};
183
184&exp2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]185 bootph-pre-ram;
Vignesh Raghavendra8a290cc2020-01-27 23:22:15 +0530[diff] [blame]186};
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]187
188&mcu_fss0_ospi0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]189 bootph-pre-ram;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]190};
191
192&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]193 bootph-pre-ram;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]194};
195
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]196&hbmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]197 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]198
199 flash@0,0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]200 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]201 };
202};
203
204&hbmc_mux {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]205 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]206};
207
208&wkup_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]209 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]210};
211
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]212&ospi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]213 bootph-pre-ram;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]214
215 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]216 bootph-pre-ram;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]217 };
218};
Keerthy71156c92020-03-04 10:09:59 +0530[diff] [blame]219
220&ospi1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]221 bootph-pre-ram;
Keerthy71156c92020-03-04 10:09:59 +0530[diff] [blame]222
223 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]224 bootph-pre-ram;
Keerthy71156c92020-03-04 10:09:59 +0530[diff] [blame]225 };
226};
227
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]228&mcu_fss0_hpb0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]229 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]230};
231
232&wkup_gpio_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]233 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]234};
235
Keerthy71156c92020-03-04 10:09:59 +0530[diff] [blame]236&mcu_fss0_ospi1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]237 bootph-pre-ram;
Keerthy71156c92020-03-04 10:09:59 +0530[diff] [blame]238};
Suman Anna90eecec2021-05-18 16:38:25 -0500[diff] [blame]239
240&main_r5fss0 {
241 ti,cluster-mode = <0>;
242};
243
244&main_r5fss1 {
245 ti,cluster-mode = <0>;
246};
Kishon Vijay Abraham I7f3a3092021-07-21 21:28:40 +0530[diff] [blame]247
248&wiz3_pll1_refclk {
249 assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
250 assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
251};
252
253&serdes_ln_ctrl {
254 u-boot,mux-autoprobe;
255};
256
257&usb_serdes_mux {
258 u-boot,mux-autoprobe;
259};
Aswath Govindrajudcfb97e2022-01-28 13:41:39 +0530[diff] [blame]260
261&serdes0 {
262 /delete-property/ assigned-clocks;
263 /delete-property/ assigned-clock-parents;
264};
265
266&serdes0_pcie_link {
267 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
268 assigned-clock-parents = <&wiz0_pll1_refclk>;
269};
Aswath Govindraju83a83672022-01-28 13:41:51 +0530[diff] [blame]270
271&serdes0_qsgmii_link {
272 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
273 assigned-clock-parents = <&wiz0_pll1_refclk>;
274};