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git01.mediatek.com / filogic / uboot / 1fc46f537af2902344ebf92b199472cdc932125d / . / arch / x86 / dts / qemu-x86_q35.dts
blob: d0830892e83bba268488ee5cce4aced46e5ba3a7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]2/*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]4 */
5
6/dts-v1/;
7
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]8#include <dt-bindings/interrupt-router/intel-irq.h>
9
10/* ICH9 IRQ router has discrete PIRQ control registers */
11#undef PIRQE
12#undef PIRQF
13#undef PIRQG
14#undef PIRQH
15#define PIRQE 8
16#define PIRQF 9
17#define PIRQG 10
18#define PIRQH 11
19
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]20/include/ "skeleton.dtsi"
21/include/ "serial.dtsi"
Bin Meng7ca73742015-11-12 05:33:06 -0800[diff] [blame]22/include/ "keyboard.dtsi"
Bin Mengaf5b8d22018-07-19 03:07:33 -0700[diff] [blame]23/include/ "reset.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +0800[diff] [blame]24/include/ "rtc.dtsi"
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]25
Bin Meng8967f632021-07-28 12:00:23 +0800[diff] [blame]26#include "tsc_timer.dtsi"
Simon Glassbee77f62020-11-05 06:32:17 -0700[diff] [blame]27#include "smbios.dtsi"
28
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]29/ {
Bin Meng000883b2015-06-03 09:20:04 +0800[diff] [blame]30 model = "QEMU x86 (Q35)";
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]31 compatible = "qemu,x86";
32
33 config {
34 silent_console = <0>;
Bin Meng70be0962015-06-03 09:20:05 +0800[diff] [blame]35 u-boot,no-apm-finalize;
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]36 };
37
38 chosen {
39 stdout-path = "/serial";
40 };
41
Bin Meng354dcdd2015-07-22 01:21:13 -0700[diff] [blame]42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
Bin Menged3fd5b2017-01-18 03:32:57 -0800[diff] [blame]45 u-boot,dm-pre-reloc;
Bin Meng354dcdd2015-07-22 01:21:13 -0700[diff] [blame]46
47 cpu@0 {
48 device_type = "cpu";
Miao Yan4336af62016-01-07 01:32:01 -0800[diff] [blame]49 compatible = "cpu-qemu";
Bin Menged3fd5b2017-01-18 03:32:57 -0800[diff] [blame]50 u-boot,dm-pre-reloc;
Bin Meng354dcdd2015-07-22 01:21:13 -0700[diff] [blame]51 reg = <0>;
52 intel,apic-id = <0>;
53 };
54 };
55
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]56 pci {
57 compatible = "pci-x86";
58 #address-cells = <3>;
59 #size-cells = <2>;
60 u-boot,dm-pre-reloc;
61 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
62 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
63 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]64
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]65 pch@1f,0 {
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]66 reg = <0x0000f800 0 0 0 0>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]67 compatible = "intel,pch9";
Bin Menged3fd5b2017-01-18 03:32:57 -0800[diff] [blame]68 u-boot,dm-pre-reloc;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]69
70 irq-router {
71 compatible = "intel,irq-router";
Bin Menged3fd5b2017-01-18 03:32:57 -0800[diff] [blame]72 u-boot,dm-pre-reloc;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]73 intel,pirq-config = "pci";
Bin Meng0651f622016-05-07 07:46:15 -0700[diff] [blame]74 intel,actl-8bit;
75 intel,actl-addr = <0x44>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]76 intel,pirq-link = <0x60 8>;
77 intel,pirq-mask = <0x0e40>;
78 intel,pirq-routing = <
79 /* e1000 NIC */
80 PCI_BDF(0, 2, 0) INTA PIRQG
81 /* ICH9 UHCI */
82 PCI_BDF(0, 29, 0) INTA PIRQA
83 PCI_BDF(0, 29, 1) INTB PIRQB
84 PCI_BDF(0, 29, 2) INTC PIRQC
85 /* ICH9 EHCI */
86 PCI_BDF(0, 29, 7) INTD PIRQD
87 /* ICH9 SATA */
88 PCI_BDF(0, 31, 2) INTA PIRQA
89 >;
90 };
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]91 };
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]92 };
93
94};